Re: [Qemu-devel] [RESEND PATCH] target/arm: change arch timer registers access permission

[Peter Maydell]

On Mon, 11 Mar 2019 at 08:29, gengdongjiu <address@hidden> wrote:
>
> From: Dongjiu Geng <address@hidden>
>
> Some generic arch timer registers are Config-RW in the EL0,
> which means the EL0 exception level can have write permission
> if it is appropriately configured.
>
> When VM access registers, it firstly checks whether they have RW
> permission, then check whether it is appropriately configured.
> If they are defined to Ready only in EL0, even though they have been

"read only" ?

> appropriately configured, they still do not have write permission.
> So need to add the write permission according to ARMV8 spec when
> define it.
>
> Signed-off-by: Dongjiu Geng <address@hidden>

Yes, this seems to be a bug which has been present since
I added the generic timer support in commit 55d284af8e31b in 2013.

I'm not sure why the bug is there -- my best guess is that I
incorrectly copied the permission flags from the CNTFRQ register
(which really is RO from PL0 but RW from PL1 and above) to
these other registers which should be fully RW from PL0.

> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 2607d39..3db94c6 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -2665,7 +2665,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
>      /* per-timer control */
>      { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 
> 1,
>        .secure = ARM_CP_SECSTATE_NS,
> -      .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
> +      .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_RW,

The PLx_{R,W,RW} constants all imply access is also possible from
the higher PLs, so this can just be written ".access = PL0_RW".

thanks
-- PMM