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Re: [Qemu-devel] [PATCH 11/11] target/hppa: call eval_interrupt() after
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 11/11] target/hppa: call eval_interrupt() after ssm |
Date: |
Tue, 12 Mar 2019 11:46:49 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 |
On 3/12/19 11:44 AM, Sven Schnelle wrote:
>> ... except what we're already doing that. So I don't see what
>> can be changed to help. This doesn't seem to make a difference.
>
> I looked into this again, and with my limited TCG knowledge it looks like the
> exit_tb is not happening because ssm is called in a branch delay slot:
>
> This is the TB it's calling when it looses the timer interrupt:
>
> IN:
> 0x0000000000045758: bv r0(rp)
> 0x000000000004575c: ssm 1,r0
>
> OP:
> ld_i32 tmp0,env,$0xffffffffffffffe0
> movi_i32 tmp1,$0x0
> brcond_i32 tmp0,tmp1,lt,$L0
>
> ---- 0000000000045758 000000000004575c
> mov_i32 tmp0,r2
> mov_i32 iaoq_b,tmp0
>
> ---- 000000000004575c 00000000ffffffff
> movi_i32 tmp1,$0x4
> add_i32 tmp0,iaoq_b,tmp1
> ld_i32 tmp1,env,$0x1c0
> movi_i32 tmp2,$0x1
> or_i32 tmp1,tmp1,tmp2
> call swap_system_mask,$0x1,$1,tmp1,env,tmp1
>
> Everything above is ssm, and below this is the branch instruction, which skips
> the exit_tb (i think):
>
> mov_i32 iaoq_f,iaoq_b
> mov_i32 iaoq_b,tmp0
> mov_i64 iasq_f,iasq_b
> call lookup_tb_ptr,$0x6,$1,tmp3,env
> goto_ptr tmp3
> set_label $L0
> exit_tb $0x7f373c33cb83
>
> I might also be totally wrong, let me know if that's the case. ;-)
You are absolutely correct. Thanks for the failing code sequence; now I know
where to look.
r~
[Qemu-devel] [PATCH 09/11] target/hppa: add TLB protection id check, Sven Schnelle, 2019/03/11
[Qemu-devel] [PATCH 06/11] target/hppa: ignore DIAG opcode, Sven Schnelle, 2019/03/11
[Qemu-devel] [PATCH 10/11] target/hppa: exit TB if either Data or Instruction TLB changes, Sven Schnelle, 2019/03/11
[Qemu-devel] [PATCH 07/11] target/hppa: fix b,gate instruction, Sven Schnelle, 2019/03/11
[Qemu-devel] [PATCH 05/11] target/hppa: remove PSW I/R/Q bit check, Sven Schnelle, 2019/03/11