[Qemu-devel] [Bug 1820686] [NEW] risc-v: 'c.unimp' instruction decoded as 'c.addi4spn fp, 0'

[Jonathan Behrens]

Public bug reported:

QEMU 3.1 incorrectly decodes the "c.unimp" instruction (opcode 0x0000)
as an "addi4spn fp, 0" when either of the two following bytes are non-
zero. This is because the ctx->opcode value used when decoding the
instruction is actually filled with a 32-bit load (to handle normal
uncompressed instructions) but when a compressed instruction is found
only the low 16 bits are valid. Other reserved/illegal bit patterns with
the addi4spn opcode are also incorrectly decoded.

I believe that the switch to decodetree on master happened to fix this
issue, but hopefully it is helpful to have this recorded somewhere. I've
included a simple one line patch if anyone wants to backport this.

** Affects: qemu
     Importance: Undecided
         Status: New

** Patch added: "decode.patch"
   
https://bugs.launchpad.net/bugs/1820686/+attachment/5247338/+files/decode.patch

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https://bugs.launchpad.net/bugs/1820686

Title:
  risc-v: 'c.unimp' instruction decoded as 'c.addi4spn fp, 0'

Status in QEMU:
  New

Bug description:
  QEMU 3.1 incorrectly decodes the "c.unimp" instruction (opcode 0x0000)
  as an "addi4spn fp, 0" when either of the two following bytes are non-
  zero. This is because the ctx->opcode value used when decoding the
  instruction is actually filled with a 32-bit load (to handle normal
  uncompressed instructions) but when a compressed instruction is found
  only the low 16 bits are valid. Other reserved/illegal bit patterns
  with the addi4spn opcode are also incorrectly decoded.

  I believe that the switch to decodetree on master happened to fix this
  issue, but hopefully it is helpful to have this recorded somewhere.
  I've included a simple one line patch if anyone wants to backport
  this.

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