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[Qemu-devel] [PATCH for 4.0 v1 0/5] Update the QEMU PLIC addresses
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH for 4.0 v1 0/5] Update the QEMU PLIC addresses |
Date: |
Thu, 21 Mar 2019 00:45:15 +0000 |
This series updates the PLIC address to match the documentation.
This fixes: https://github.com/riscv/opensbi/issues/97
Alistair Francis (5):
riscv: plic: Fix incorrect irq calculation
riscv: sifive_u: Fix PLIC priority base offset and numbering
riscv: sifive_e: Fix PLIC priority base offset
riscv: virt: Fix PLIC priority base offset
riscv: plic: Log guest errors
hw/riscv/sifive_plic.c | 16 +++++++++++-----
hw/riscv/sifive_u.c | 2 +-
include/hw/riscv/sifive_e.h | 2 +-
include/hw/riscv/sifive_u.h | 4 ++--
include/hw/riscv/virt.h | 2 +-
5 files changed, 16 insertions(+), 10 deletions(-)
--
2.21.0
- [Qemu-devel] [PATCH for 4.0 v1 0/5] Update the QEMU PLIC addresses,
Alistair Francis <=
[Qemu-devel] [PATCH for 4.0 v1 3/5] riscv: sifive_e: Fix PLIC priority base offset, Alistair Francis, 2019/03/20