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[Qemu-devel] [RFC PATCH 14/17] convert cadence_uart to 3-phases reset
From: |
Damien Hedde |
Subject: |
[Qemu-devel] [RFC PATCH 14/17] convert cadence_uart to 3-phases reset |
Date: |
Mon, 25 Mar 2019 12:01:57 +0100 |
Split the existing reset procedure into 3 phases.
Test the resetting flag to discard register accesses
and character reception.
Also adds a active high reset io.
Signed-off-by: Damien Hedde <address@hidden>
---
hw/char/cadence_uart.c | 48 ++++++++++++++++++++++++++++++++++++++----
1 file changed, 44 insertions(+), 4 deletions(-)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index fbdbd463bb..694c8ea614 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -222,6 +222,10 @@ static int uart_can_receive(void *opaque)
int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
+ if (qdev_is_resetting((DeviceState *) opaque)) {
+ return 0;
+ }
+
if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count);
}
@@ -337,6 +341,10 @@ static void uart_receive(void *opaque, const uint8_t *buf,
int size)
CadenceUARTState *s = opaque;
uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
+ if (qdev_is_resetting((DeviceState *) opaque)) {
+ return;
+ }
+
if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
uart_write_rx_fifo(opaque, buf, size);
}
@@ -350,6 +358,10 @@ static void uart_event(void *opaque, int event)
CadenceUARTState *s = opaque;
uint8_t buf = '\0';
+ if (qdev_is_resetting((DeviceState *) opaque)) {
+ return;
+ }
+
if (event == CHR_EVENT_BREAK) {
uart_write_rx_fifo(opaque, &buf, 1);
}
@@ -382,6 +394,10 @@ static void uart_write(void *opaque, hwaddr offset,
{
CadenceUARTState *s = opaque;
+ if (qdev_is_resetting((DeviceState *)opaque)) {
+ return;
+ }
+
DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
offset >>= 2;
if (offset >= CADENCE_UART_R_MAX) {
@@ -440,6 +456,10 @@ static uint64_t uart_read(void *opaque, hwaddr offset,
CadenceUARTState *s = opaque;
uint32_t c = 0;
+ if (qdev_is_resetting((DeviceState *)opaque)) {
+ return 0;
+ }
+
offset >>= 2;
if (offset >= CADENCE_UART_R_MAX) {
c = 0;
@@ -459,9 +479,9 @@ static const MemoryRegionOps uart_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void cadence_uart_reset(DeviceState *dev)
+static void cadence_uart_reset_init(Object *obj, bool cold)
{
- CadenceUARTState *s = CADENCE_UART(dev);
+ CadenceUARTState *s = CADENCE_UART(obj);
s->r[R_CR] = 0x00000128;
s->r[R_IMR] = 0;
@@ -470,6 +490,18 @@ static void cadence_uart_reset(DeviceState *dev)
s->r[R_BRGR] = 0x0000028B;
s->r[R_BDIV] = 0x0000000F;
s->r[R_TTRIG] = 0x00000020;
+}
+
+static void cadence_uart_reset_hold(Object *obj)
+{
+ CadenceUARTState *s = CADENCE_UART(obj);
+
+ qemu_set_irq(s->irq, 0);
+}
+
+static void cadence_uart_reset_exit(Object *obj)
+{
+ CadenceUARTState *s = CADENCE_UART(obj);
uart_rx_reset(s);
uart_tx_reset(s);
@@ -498,6 +530,8 @@ static void cadence_uart_init(Object *obj)
sysbus_init_irq(sbd, &s->irq);
s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
+
+ qdev_init_warm_reset_gpio(DEVICE(obj), "rst", DEVICE_ACTIVE_HIGH);
}
static int cadence_uart_post_load(void *opaque, int version_id)
@@ -532,6 +566,10 @@ static const VMStateDescription vmstate_cadence_uart = {
VMSTATE_UINT32(rx_wpos, CadenceUARTState),
VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
VMSTATE_END_OF_LIST()
+ },
+ .subsections = (const VMStateDescription * []) {
+ &device_vmstate_reset,
+ NULL
}
};
@@ -546,9 +584,11 @@ static void cadence_uart_class_init(ObjectClass *klass,
void *data)
dc->realize = cadence_uart_realize;
dc->vmsd = &vmstate_cadence_uart;
- dc->reset = cadence_uart_reset;
+ dc->reset_phases.init = cadence_uart_reset_init;
+ dc->reset_phases.hold = cadence_uart_reset_hold;
+ dc->reset_phases.exit = cadence_uart_reset_exit;
dc->props = cadence_uart_properties;
- }
+}
static const TypeInfo cadence_uart_info = {
.name = TYPE_CADENCE_UART,
--
2.21.0
- [Qemu-devel] [RFC PATCH 03/17] make Device and Bus Resettable, (continued)
- [Qemu-devel] [RFC PATCH 03/17] make Device and Bus Resettable, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 09/17] global ResetDomain support for legacy reset handlers, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 10/17] Delete the system ResetDomain at the end of emulation, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 04/17] Add local reset methods in Device class, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 05/17] add vmstate description for device reset state, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 06/17] Add function to control reset with gpio inputs, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 01/17] Create Resettable QOM interface, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 11/17] Put orphan buses in system reset domain, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 12/17] Put default sysbus in system reset domain, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 17/17] Connect the uart reset gpios in the zynq platform, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 14/17] convert cadence_uart to 3-phases reset,
Damien Hedde <=
- [Qemu-devel] [RFC PATCH 16/17] Add uart reset support in zynq_slcr, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 13/17] hw/misc/zynq_slcr: use standard register definition, Damien Hedde, 2019/03/25
- [Qemu-devel] [RFC PATCH 15/17] Convert zynq's slcr to 3-phases reset, Damien Hedde, 2019/03/25
- Re: [Qemu-devel] [RFC 00/17] multi-phase reset mechanism, no-reply, 2019/03/25