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Re: [Qemu-devel] [PATCH for 4.0 v1 5/5] riscv: plic: Log guest errors
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH for 4.0 v1 5/5] riscv: plic: Log guest errors |
Date: |
Wed, 27 Mar 2019 00:23:56 +0100 |
Le jeu. 21 mars 2019 02:00, Alistair Francis <address@hidden> a
écrit :
> Instead of using error_report() to print guest errors let's use
> qemu_log_mask(LOG_GUEST_ERROR,...) to log the error.
>
> Signed-off-by: Alistair Francis <address@hidden>
> ---
> hw/riscv/sifive_plic.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
> index 70a85cd075..7f373d6c9d 100644
> --- a/hw/riscv/sifive_plic.c
> +++ b/hw/riscv/sifive_plic.c
> @@ -262,7 +262,9 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr
> addr, unsigned size)
> }
>
> err:
> - error_report("plic: invalid register read: %08x", (uint32_t)addr);
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
> + __func__, addr);
> return 0;
> }
>
> @@ -289,7 +291,9 @@ static void sifive_plic_write(void *opaque, hwaddr
> addr, uint64_t value,
> } else if (addr >= plic->pending_base && /* 1 bit per source */
> addr < plic->pending_base + (plic->num_sources >> 3))
> {
> - error_report("plic: invalid pending write: %08x", (uint32_t)addr);
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: invalid pending write: 0x%" HWADDR_PRIx "",
> + __func__, addr);
> return;
> } else if (addr >= plic->enable_base && /* 1 bit per source */
> addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
> @@ -339,7 +343,9 @@ static void sifive_plic_write(void *opaque, hwaddr
> addr, uint64_t value,
> }
>
> err:
> - error_report("plic: invalid register write: %08x", (uint32_t)addr);
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
> + __func__, addr);
> }
>
> static const MemoryRegionOps sifive_plic_ops = {
> --
> 2.21.0
>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
>
- [Qemu-devel] [PATCH for 4.0 v1 0/5] Update the QEMU PLIC addresses, Alistair Francis, 2019/03/20
- [Qemu-devel] [PATCH for 4.0 v1 5/5] riscv: plic: Log guest errors, Alistair Francis, 2019/03/20
- [Qemu-devel] [PATCH for 4.0 v1 4/5] riscv: virt: Fix PLIC priority base offset, Alistair Francis, 2019/03/20
- [Qemu-devel] [PATCH for 4.0 v1 2/5] riscv: sifive_u: Fix PLIC priority base offset and numbering, Alistair Francis, 2019/03/20
- [Qemu-devel] [PATCH for 4.0 v1 1/5] riscv: plic: Fix incorrect irq calculation, Alistair Francis, 2019/03/20
- [Qemu-devel] [PATCH for 4.0 v1 3/5] riscv: sifive_e: Fix PLIC priority base offset, Alistair Francis, 2019/03/20
- Re: [Qemu-devel] [PATCH for 4.0 v1 0/5] Update the QEMU PLIC addresses, Alistair Francis, 2019/03/26
- Message not available
- Re: [Qemu-devel] [PATCH for 4.0 v1 5/5] riscv: plic: Log guest errors,
Philippe Mathieu-Daudé <=