[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH for-4.1 1/8] target/riscv: Name the argument sets fo
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH for-4.1 1/8] target/riscv: Name the argument sets for all of insn32 formats |
Date: |
Mon, 1 Apr 2019 10:11:48 +0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/riscv/insn32.decode | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6f3ab7aa52..77f794ed70 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -34,9 +34,13 @@
%imm_u 12:s20 !function=ex_shift_12
# Argument sets:
+&empty
&b imm rs2 rs1
&i imm rs1 rd
+&j imm rd
&r rd rs1 rs2
+&s imm rs1 rs2
+&u imm rd
&shift shamt rs1 rd
&atomic aq rl rs2 rs1 rd
@@ -44,9 +48,9 @@
@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1
%rd
@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1
%rd
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
address@hidden ....... ..... ..... ... ..... ....... imm=%imm_s
%rs2 %rs1
address@hidden .................... ..... ....... imm=%imm_u
%rd
address@hidden .................... ..... ....... imm=%imm_j
%rd
address@hidden ....... ..... ..... ... ..... ....... &s imm=%imm_s
%rs2 %rs1
address@hidden .................... ..... ....... &u imm=%imm_u
%rd
address@hidden .................... ..... ....... &j imm=%imm_j
%rd
@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1
%rd
@csr ............ ..... ... ..... ....... %csr %rs1
%rd
--
2.17.1
- [Qemu-devel] [PATCH for-4.1 0/8] target/riscv: decodetree improvments, Richard Henderson, 2019/03/31
- [Qemu-devel] [PATCH for-4.1 1/8] target/riscv: Name the argument sets for all of insn32 formats,
Richard Henderson <=
- [Qemu-devel] [PATCH for-4.1 2/8] target/riscv: Use --static-decode for decodetree, Richard Henderson, 2019/03/31
- [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16, Richard Henderson, 2019/03/31
- [Qemu-devel] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti, Richard Henderson, 2019/03/31
- [Qemu-devel] [PATCH for-4.1 5/8] target/riscv: Use pattern groups in insn16.decode, Richard Henderson, 2019/03/31
- [Qemu-devel] [PATCH for-4.1 6/8] target/riscv: Split RVC32 and RVC64 insns into separate files, Richard Henderson, 2019/03/31
- [Qemu-devel] [PATCH for-4.1 7/8] target/riscv: Split gen_arith_imm into functional and temp, Richard Henderson, 2019/03/31
- [Qemu-devel] [PATCH for-4.1 8/8] target/riscv: Remove spaces from register names, Richard Henderson, 2019/03/31