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[Qemu-devel] [PATCH 04/26] target/arm: Disable most VFP sysregs for M-pr
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 04/26] target/arm: Disable most VFP sysregs for M-profile |
Date: |
Tue, 16 Apr 2019 13:57:22 +0100 |
The only "system register" that M-profile floating point exposes
via the VMRS/VMRS instructions is FPSCR, and it does not have
the odd special case for rd==15. Add a check to ensure we only
expose FPSCR.
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d408e4d7ef4..d56488ec847 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -3512,12 +3512,27 @@ static int disas_vfp_insn(DisasContext *s, uint32_t
insn)
}
}
} else { /* !dp */
+ bool is_sysreg;
+
if ((insn & 0x6f) != 0x00)
return 1;
rn = VFP_SREG_N(insn);
+
+ is_sysreg = extract32(insn, 21, 1);
+
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
+ /*
+ * The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
+ * Writes to R15 are UNPREDICTABLE; we choose to undef.
+ */
+ if (is_sysreg && (rd == 15 || (rn >> 1) != ARM_VFP_FPSCR))
{
+ return 1;
+ }
+ }
+
if (insn & ARM_CP_RW_BIT) {
/* vfp->arm */
- if (insn & (1 << 21)) {
+ if (is_sysreg) {
/* system register */
rn >>= 1;
@@ -3584,7 +3599,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
}
} else {
/* arm->vfp */
- if (insn & (1 << 21)) {
+ if (is_sysreg) {
rn >>= 1;
/* system register */
switch (rn) {
--
2.20.1
- [Qemu-devel] [PATCH 00/26] target/arm: Implement M profile floating point, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 01/26] target/arm: Make sure M-profile FPSCR RES0 bits are not settable, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 03/26] target/arm: Implement dummy versions of M-profile FP-related registers, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 02/26] hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registers, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 04/26] target/arm: Disable most VFP sysregs for M-profile,
Peter Maydell <=
- [Qemu-devel] [PATCH 06/26] target/arm: Decode FP instructions for M profile, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 07/26] target/arm: Clear CONTROL_S.SFPA in SG insn if FPU present, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 09/26] target/arm/helper: don't return early for STKOF faults during stacking, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 10/26] target/arm: Handle floating point registers in exception entry, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 05/26] target/arm: Honour M-profile FP enable bits, Peter Maydell, 2019/04/16