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[Qemu-devel] [PATCH v9 6/6] target/mips: Merge implementation of ILVOD.D
From: |
Mateja Marjanovic |
Subject: |
[Qemu-devel] [PATCH v9 6/6] target/mips: Merge implementation of ILVOD.D and ILVL.D |
Date: |
Thu, 18 Apr 2019 17:29:10 +0200 |
From: Mateja Marjanovic <address@hidden>
The implementation for ILVOD.D and ILVL.D instructions
is equivalent, so use a single handler for both of them.
Suggested-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Mateja Marjanovic <address@hidden>
---
target/mips/translate.c | 27 ++++++++++-----------------
1 file changed, 10 insertions(+), 17 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 019a2c0..020a659 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28310,19 +28310,6 @@ static inline void gen_ilvl_w(CPUMIPSState *env,
uint32_t wd,
}
/*
- * [MSA] ILVL.D wd, ws, wt
- *
- * Vector Interleave Left (doubleword data elements)
- *
- */
-static inline void gen_ilvl_d(CPUMIPSState *env, uint32_t wd,
- uint32_t ws, uint32_t wt)
-{
- tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2 + 1]);
- tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2 + 1]);
-}
-
-/*
* [MSA] ILVOD.<B|H> wd, ws, wt
*
* Vector Interleave Odd (<byte|halfword> data elements)
@@ -28388,9 +28375,15 @@ static inline void gen_ilvod_w(CPUMIPSState *env,
uint32_t wd,
*
* Vector Interleave Odd (doubleword data elements)
*
+ * [MSA] ILVL.D wd, ws, wt
+ *
+ * Vector Interleave Left (doubleword data elements)
+ *
+ * These two instructions are functionally equivalent.
+ *
*/
-static inline void gen_ilvod_d(CPUMIPSState *env, uint32_t wd,
- uint32_t ws, uint32_t wt)
+static inline void gen_ilvod_ilvl_d(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
{
tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2 + 1]);
tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2 + 1]);
@@ -28603,7 +28596,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext
*ctx)
gen_ilvl_w(env, wd, ws, wt);
break;
case DF_DOUBLE:
- gen_ilvl_d(env, wd, ws, wt);
+ gen_ilvod_ilvl_d(env, wd, ws, wt);
break;
default:
assert(0);
@@ -28699,7 +28692,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext
*ctx)
gen_ilvod_w(env, wd, ws, wt);
break;
case DF_DOUBLE:
- gen_ilvod_d(env, wd, ws, wt);
+ gen_ilvod_ilvl_d(env, wd, ws, wt);
break;
default:
assert(0);
--
2.7.4
- [Qemu-devel] [PATCH v9 0/6] target/mips: Optimize MSA interleave instructions, Mateja Marjanovic, 2019/04/18
- [Qemu-devel] [PATCH v9 5/6] target/mips: Merge implementation of ILVEV.D and ILVR.D, Mateja Marjanovic, 2019/04/18
- [Qemu-devel] [PATCH v9 3/6] target/mips: Optimize ILVL.<B|H|W|D> MSA instructions, Mateja Marjanovic, 2019/04/18
- [Qemu-devel] [PATCH v9 6/6] target/mips: Merge implementation of ILVOD.D and ILVL.D,
Mateja Marjanovic <=
- [Qemu-devel] [PATCH v9 1/6] target/mips: Optimize ILVOD.<B|H|W|D> MSA instructions, Mateja Marjanovic, 2019/04/18
- [Qemu-devel] [PATCH v9 4/6] target/mips: Optimize ILVR.<B|H|W|D> MSA instructions, Mateja Marjanovic, 2019/04/18
- [Qemu-devel] [PATCH v9 2/6] target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions, Mateja Marjanovic, 2019/04/18
- Re: [Qemu-devel] [PATCH v9 0/6] target/mips: Optimize MSA interleave instructions, no-reply, 2019/04/18
- Re: [Qemu-devel] [PATCH v9 0/6] target/mips: Optimize MSA interleave instructions, no-reply, 2019/04/18