[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v9 0/6] target/mips: Optimize MSA interleave instruc
From: |
Mateja Marjanovic |
Subject: |
[Qemu-devel] [PATCH v9 0/6] target/mips: Optimize MSA interleave instructions |
Date: |
Thu, 18 Apr 2019 17:29:04 +0200 |
From: Mateja Marjanovic <address@hidden>
Optimize and refactor MSA instructions ILVEV.<B|H|W|D>,
ILVOD.<B|H|W|D>, ILVL.<B|H|W|D> and ILVR.<B|H|W|D>.
v9:
- Tests were changed, instead of iterating through the
loop 10 million times and calling the instruction
once, iterate through the loop 1 million times, and
call the instruction ten times.
- Eliminate the hybrid approach in ILVL.<B|H|W|D> and
ILVR.<B|H|W|D>, because the performance of directly
using TCG registers is much better than the
performance of the handler.
- Change the tables in the commit messages, due to
modified performance testing program.
v8:
- Rebased onto current master branch.
- Inserted Reviewed-by in the applicable commit message.
v7:
- Use tcg constants, instead of uint64_t constants in
ILVEV.<B|H> and ILVOD.<B|H> instructions.
- Refactor gen_ilvod_b and gen_ilvod_h functions. Use
the shared function gen_ilvod_bh, which has two extra
arguments mask and shift, because mask and shift are
the only differences in the implementation of those
two functions.
Same applies for gen_ilvev_b and gen_ilvev_h.
- Use assigning uint64_t constant values to the bit mask,
instead of shifting the bit mask, in ILVR.<H|W> and
ILVL.<H|W> instructions.
- Use only one helper for ILVEV.D and ILVR.D instructions,
because they are equivalent.
Same applies for ILVOD.D and ILVL.D.
- Minor changes in the commit messages.
v6:
- Add ILVL.<B|H|W|D> and ILVR.<B|H|W|D> MSA instructions
with mixed approaches (with helpers and with tcg
registers).
- Test the performance for ILVL.<B|H|W|D> and
ILVR.<B|H|W|D> MSA instructions, with helpers,
with tcg and with the mixed approach.
- Use a tcg register instead of an int variable for
storing a constant value of the mask (for logic
operations).
- Eliminate some unnecessary tcg_gen calls.
- Changes in commit messages and the cover letter.
v5:
- Use tcg_gen_deposit function.
- Added performance number for no-deposit and
with-deposit cases of ILVEV.W.
- Minor changes in commit messages and the cover letter.
v4:
- Clean up typing errors.
- Change the commit message and the cover letter.
- Fix bug for ILVEV.D, in case where the destination
and one of the sources are the same register.
v3:
- Reduce the number of logic operations to a
minimum.
- Add comments.
v2:
- Minor changes in commit messages and the cover letter.
Mateja Marjanovic (6):
target/mips: Optimize ILVOD.<B|H|W|D> MSA instructions
target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions
target/mips: Optimize ILVL.<B|H|W|D> MSA instructions
target/mips: Optimize ILVR.<B|H|W|D> MSA instructions
target/mips: Merge implementation of ILVEV.D and ILVR.D
target/mips: Merge implementation of ILVOD.D and ILVL.D
target/mips/helper.h | 4 -
target/mips/msa_helper.c | 32 ---
target/mips/translate.c | 532 ++++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 528 insertions(+), 40 deletions(-)
--
2.7.4
- [Qemu-devel] [PATCH v9 0/6] target/mips: Optimize MSA interleave instructions,
Mateja Marjanovic <=
- [Qemu-devel] [PATCH v9 5/6] target/mips: Merge implementation of ILVEV.D and ILVR.D, Mateja Marjanovic, 2019/04/18
- [Qemu-devel] [PATCH v9 3/6] target/mips: Optimize ILVL.<B|H|W|D> MSA instructions, Mateja Marjanovic, 2019/04/18
- [Qemu-devel] [PATCH v9 6/6] target/mips: Merge implementation of ILVOD.D and ILVL.D, Mateja Marjanovic, 2019/04/18
- [Qemu-devel] [PATCH v9 1/6] target/mips: Optimize ILVOD.<B|H|W|D> MSA instructions, Mateja Marjanovic, 2019/04/18
- [Qemu-devel] [PATCH v9 4/6] target/mips: Optimize ILVR.<B|H|W|D> MSA instructions, Mateja Marjanovic, 2019/04/18
- [Qemu-devel] [PATCH v9 2/6] target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions, Mateja Marjanovic, 2019/04/18
- Re: [Qemu-devel] [PATCH v9 0/6] target/mips: Optimize MSA interleave instructions, no-reply, 2019/04/18
- Re: [Qemu-devel] [PATCH v9 0/6] target/mips: Optimize MSA interleave instructions, no-reply, 2019/04/18