[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v1 1/8] target/riscv: Mark privilege level 2 as rese
|
From: |
Alistair Francis |
|
Subject: |
[Qemu-devel] [PATCH v1 1/8] target/riscv: Mark privilege level 2 as reserved |
|
Date: |
Sat, 20 Apr 2019 02:26:45 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_bits.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7180fccf54..945aa8dbb8 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -383,7 +383,7 @@
/* Privilege modes */
#define PRV_U 0
#define PRV_S 1
-#define PRV_H 2
+#define PRV_H 2 /* Reserved */
#define PRV_M 3
/* RV32 satp CSR field masks */
--
2.21.0
- [Qemu-devel] [PATCH v1 0/8] RISC-V: Add some prep patches for the Hypervisor, Alistair Francis, 2019/04/19
- [Qemu-devel] [PATCH v1 1/8] target/riscv: Mark privilege level 2 as reserved,
Alistair Francis <=
- [Qemu-devel] [PATCH v1 2/8] target/riscv: Trigger interrupt on MIP update asynchronously, Alistair Francis, 2019/04/19
- [Qemu-devel] [PATCH v1 3/8] target/riscv: Improve the scause logic, Alistair Francis, 2019/04/19
- [Qemu-devel] [PATCH v1 5/8] target/riscv: Allow setting mstatus virtulisation bits, Alistair Francis, 2019/04/19
- [Qemu-devel] [PATCH v1 4/8] target/riscv: Add the MPV and MTL mstatus bits, Alistair Francis, 2019/04/19
- [Qemu-devel] [PATCH v1 6/8] target/riscv: Add Hypervisor CSR macros, Alistair Francis, 2019/04/19
- [Qemu-devel] [PATCH v1 7/8] target/riscv: Add the HSTATUS register masks, Alistair Francis, 2019/04/19
- [Qemu-devel] [PATCH v1 8/8] target/riscv: Add the HGATP register masks, Alistair Francis, 2019/04/19