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[Qemu-devel] [PULL 15/42] target/arm: Clear CONTROL.SFPA in BXNS and BLX
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 15/42] target/arm: Clear CONTROL.SFPA in BXNS and BLXNS |
Date: |
Mon, 29 Apr 2019 18:00:03 +0100 |
For v8M floating point support, transitions from Secure
to Non-secure state via BLNS and BLXNS must clear the
CONTROL.SFPA bit. (This corresponds to the pseudocode
BranchToNS() function.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/helper.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 547898581a2..088852ceb96 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7819,6 +7819,9 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
/* translate.c should have made BXNS UNDEF unless we're secure */
assert(env->v7m.secure);
+ if (!(dest & 1)) {
+ env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK;
+ }
switch_v7m_security_state(env, dest & 1);
env->thumb = 1;
env->regs[15] = dest & ~1;
@@ -7876,6 +7879,7 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
*/
write_v7m_exception(env, 1);
}
+ env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK;
switch_v7m_security_state(env, 0);
env->thumb = 1;
env->regs[15] = dest;
--
2.20.1
- [Qemu-devel] [PULL 00/42] target-arm queue, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 02/42] hw/ssi/xilinx_spips: Avoid variable length array, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 06/42] target/arm: Implement dummy versions of M-profile FP-related registers, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 05/42] hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registers, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 03/42] configure: Remove --source-path option, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 01/42] hw/arm/smmuv3: Remove SMMUNotifierNode, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 07/42] target/arm: Disable most VFP sysregs for M-profile, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 15/42] target/arm: Clear CONTROL.SFPA in BXNS and BLXNS,
Peter Maydell <=
- [Qemu-devel] [PULL 17/42] target/arm: Allow for floating point in callee stack integrity check, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 13/42] target/arm: Handle floating point registers in exception entry, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 09/42] target/arm: Decode FP instructions for M profile, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 21/42] target/arm: Set FPCCR.S when executing M-profile floating point insns, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 08/42] target/arm: Honour M-profile FP enable bits, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 22/42] target/arm: Activate M-profile floating point context when FPCCR.ASPEN is set, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 24/42] target/arm: New function armv7m_nvic_set_pending_lazyfp(), Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 30/42] hw/dma: Compile the bcm2835_dma device as common object, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 32/42] hw/arm/nseries: Use TYPE_TMP105 instead of hardcoded string, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 04/42] target/arm: Make sure M-profile FPSCR RES0 bits are not settable, Peter Maydell, 2019/04/29