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[Qemu-devel] [PULL 23/42] target/arm: New helper function arm_v7m_mmu_id
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 23/42] target/arm: New helper function arm_v7m_mmu_idx_all() |
Date: |
Mon, 29 Apr 2019 18:00:11 +0100 |
Add a new helper function which returns the MMU index to use
for v7M, where the caller specifies all of the security
state, privilege level and whether the execution priority
is negative, and reimplement the existing
arm_v7m_mmu_idx_for_secstate_and_priv() in terms of it.
We are going to need this for the lazy-FP-stacking code.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/cpu.h | 7 +++++++
target/arm/helper.c | 14 +++++++++++---
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d4996a4d204..920cf367020 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2911,6 +2911,13 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
}
}
+/*
+ * Return the MMU index for a v7M CPU with all relevant information
+ * manually specified.
+ */
+ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+ bool secstate, bool priv, bool negpri);
+
/* Return the MMU index for a v7M CPU in the specified security and
* privilege state.
*/
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 84e3790a9de..1ed5f1a2513 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -13230,8 +13230,8 @@ int fp_exception_el(CPUARMState *env, int cur_el)
return 0;
}
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
- bool secstate, bool priv)
+ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+ bool secstate, bool priv, bool negpri)
{
ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
@@ -13239,7 +13239,7 @@ ARMMMUIdx
arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
mmu_idx |= ARM_MMU_IDX_M_PRIV;
}
- if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) {
+ if (negpri) {
mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
}
@@ -13250,6 +13250,14 @@ ARMMMUIdx
arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
return mmu_idx;
}
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+ bool secstate, bool priv)
+{
+ bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
+
+ return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
+}
+
/* Return the MMU index for a v7M CPU in the specified security state */
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
{
--
2.20.1
- [Qemu-devel] [PULL 27/42] target/arm: Implement VLSTM for v7M CPUs with an FPU, (continued)
- [Qemu-devel] [PULL 27/42] target/arm: Implement VLSTM for v7M CPUs with an FPU, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 34/42] hw/devices: Move TC6393XB declarations into a new header, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 20/42] target/arm: Overlap VECSTRIDE and XSCALE_CPAR TB flags, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 11/42] target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 38/42] hw/devices: Move TI touchscreen declarations into a new header, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 19/42] target/arm: Move NS TBFLAG from bit 19 to bit 6, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 39/42] hw/devices: Move LAN9118 declarations into a new header, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 35/42] hw/devices: Move Blizzard declarations into a new header, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 18/42] target/arm: Handle floating point registers in exception return, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 42/42] hw/devices: Move SMSC 91C111 declaration into a new header, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 23/42] target/arm: New helper function arm_v7m_mmu_idx_all(),
Peter Maydell <=
- [Qemu-devel] [PULL 37/42] hw/devices: Move Gamepad declarations into a new header, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 26/42] target/arm: Implement M-profile lazy FP state preservation, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 36/42] hw/devices: Move CBus declarations into a new header, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 29/42] target/arm: Enable FPU for Cortex-M4 and Cortex-M33, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 40/42] hw/net/ne2000-isa: Add guards to the header, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 33/42] hw/display/tc6393xb: Remove unused functions, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 25/42] target/arm: Add lazy-FP-stacking support to v7m_stack_write(), Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 14/42] target/arm: Implement v7m_update_fpccr(), Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 31/42] hw/arm/aspeed: Use TYPE_TMP105/TYPE_PCA9552 instead of hardcoded string, Peter Maydell, 2019/04/29
- Re: [Qemu-devel] [PULL 00/42] target-arm queue, Peter Maydell, 2019/04/29