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Re: [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID chang


From: Palmer Dabbelt
Subject: Re: [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes
Date: Wed, 08 May 2019 13:42:12 -0700 (PDT)

On Wed, 08 May 2019 10:38:35 PDT (-0700), address@hidden wrote:
There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857

Signed-off-by: Jonathan Behrens <address@hidden>
---
 target/riscv/csr.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6083c782a1..1ec1222da1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -732,7 +732,9 @@ static int write_satp(CPURISCVState *env, int csrno, 
target_ulong val)
         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
             return -1;
         } else {
-            tlb_flush(CPU(riscv_env_get_cpu(env)));
+            if((val ^ env->satp) & SATP_ASID) {
+                tlb_flush(CPU(riscv_env_get_cpu(env)));
+            }
             env->satp = val;
         }
     }

Thanks!  I've taken this into my for-master branch, pending some testing I'll
send it up.



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