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[Qemu-devel] [PULL 11/27] target/mips: Tidy control flow in mips_cpu_han
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 11/27] target/mips: Tidy control flow in mips_cpu_handle_mmu_fault |
Date: |
Fri, 10 May 2019 08:19:28 -0700 |
Since the only non-negative TLBRET_* value is TLBRET_MATCH,
the subsequent test for ret < 0 is useless. Use early return
to allow subsequent blocks to be unindented.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/mips/helper.c | 54 ++++++++++++++++++++------------------------
1 file changed, 24 insertions(+), 30 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index cc7be7703a..86e622efb8 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -915,41 +915,35 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr
address, int size, int rw,
tlb_set_page(cs, address & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
mmu_idx, TARGET_PAGE_SIZE);
- ret = 0;
- } else if (ret < 0)
-#endif
- {
-#if !defined(CONFIG_USER_ONLY)
+ return 0;
+ }
#if !defined(TARGET_MIPS64)
- if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) {
- /*
- * Memory reads during hardware page table walking are performed
- * as if they were kernel-mode load instructions.
- */
- int mode = (env->hflags & MIPS_HFLAG_KSU);
- bool ret_walker;
- env->hflags &= ~MIPS_HFLAG_KSU;
- ret_walker = page_table_walk_refill(env, address, rw, mmu_idx);
- env->hflags |= mode;
- if (ret_walker) {
- ret = get_physical_address(env, &physical, &prot,
- address, rw, access_type, mmu_idx);
- if (ret == TLBRET_MATCH) {
- tlb_set_page(cs, address & TARGET_PAGE_MASK,
- physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
- mmu_idx, TARGET_PAGE_SIZE);
- ret = 0;
- return ret;
- }
+ if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) {
+ /*
+ * Memory reads during hardware page table walking are performed
+ * as if they were kernel-mode load instructions.
+ */
+ int mode = (env->hflags & MIPS_HFLAG_KSU);
+ bool ret_walker;
+ env->hflags &= ~MIPS_HFLAG_KSU;
+ ret_walker = page_table_walk_refill(env, address, rw, mmu_idx);
+ env->hflags |= mode;
+ if (ret_walker) {
+ ret = get_physical_address(env, &physical, &prot,
+ address, rw, access_type, mmu_idx);
+ if (ret == TLBRET_MATCH) {
+ tlb_set_page(cs, address & TARGET_PAGE_MASK,
+ physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
+ mmu_idx, TARGET_PAGE_SIZE);
+ return 0;
}
}
-#endif
-#endif
- raise_mmu_exception(env, address, rw, ret);
- ret = 1;
}
+#endif
+#endif
- return ret;
+ raise_mmu_exception(env, address, rw, ret);
+ return 1;
}
#if !defined(CONFIG_USER_ONLY)
--
2.17.1
- [Qemu-devel] [PULL 05/27] target/hppa: Convert to CPUClass::tlb_fill, (continued)
- [Qemu-devel] [PULL 05/27] target/hppa: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 06/27] target/i386: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 01/27] tcg: Add CPUClass::tlb_fill, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 04/27] target/cris: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 07/27] target/lm32: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 09/27] target/microblaze: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 10/27] target/mips: Pass a valid error to raise_mmu_exception for user-only, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 12/27] target/mips: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 13/27] target/moxie: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 08/27] target/m68k: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 11/27] target/mips: Tidy control flow in mips_cpu_handle_mmu_fault,
Richard Henderson <=
- [Qemu-devel] [PULL 14/27] target/nios2: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 15/27] target/openrisc: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 18/27] target/s390x: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 17/27] target/riscv: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 16/27] target/ppc: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 21/27] target/tilegx: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 19/27] target/sh4: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 20/27] target/sparc: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 22/27] target/tricore: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10
- [Qemu-devel] [PULL 23/27] target/unicore32: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/05/10