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[Qemu-devel] [PATCH v11 11/12] Add rx-softmmu
From: |
Yoshinori Sato |
Subject: |
[Qemu-devel] [PATCH v11 11/12] Add rx-softmmu |
Date: |
Mon, 13 May 2019 14:25:17 +0900 |
From: Yoshinori Sato <address@hidden>
Signed-off-by: Yoshinori Sato <address@hidden>
Signed-off-by: Yoshinori Sato <address@hidden>
---
arch_init.c | 2 ++
configure | 8 ++++++++
default-configs/rx-softmmu.mak | 3 +++
hw/Kconfig | 1 +
include/sysemu/arch_init.h | 1 +
5 files changed, 15 insertions(+)
create mode 100644 default-configs/rx-softmmu.mak
diff --git a/arch_init.c b/arch_init.c
index f4f3f610c8..cc25ddd7ca 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -74,6 +74,8 @@ int graphic_depth = 32;
#define QEMU_ARCH QEMU_ARCH_PPC
#elif defined(TARGET_RISCV)
#define QEMU_ARCH QEMU_ARCH_RISCV
+#elif defined(TARGET_RX)
+#define QEMU_ARCH QEMU_ARCH_RX
#elif defined(TARGET_S390X)
#define QEMU_ARCH QEMU_ARCH_S390X
#elif defined(TARGET_SH4)
diff --git a/configure b/configure
index 63f312bd1f..142827b743 100755
--- a/configure
+++ b/configure
@@ -7547,6 +7547,11 @@ case "$target_name" in
gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml"
target_compiler=$cross_cc_riscv64
;;
+ rx)
+ TARGET_ARCH=rx
+ bflt="yes"
+ target_compiler=$cross_cc_rx
+ ;;
sh4|sh4eb)
TARGET_ARCH=sh4
bflt="yes"
@@ -7767,6 +7772,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
riscv*)
disas_config "RISCV"
;;
+ rx)
+ disas_config "RX"
+ ;;
s390*)
disas_config "S390"
;;
diff --git a/default-configs/rx-softmmu.mak b/default-configs/rx-softmmu.mak
new file mode 100644
index 0000000000..a3eecefb11
--- /dev/null
+++ b/default-configs/rx-softmmu.mak
@@ -0,0 +1,3 @@
+# Default configuration for rx-softmmu
+
+CONFIG_RX_VIRT=y
diff --git a/hw/Kconfig b/hw/Kconfig
index 88b9f15007..63a071092e 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -53,6 +53,7 @@ source nios2/Kconfig
source openrisc/Kconfig
source ppc/Kconfig
source riscv/Kconfig
+source rx/Kconfig
source s390x/Kconfig
source sh4/Kconfig
source sparc/Kconfig
diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
index 10cbafe970..3f4f844f7b 100644
--- a/include/sysemu/arch_init.h
+++ b/include/sysemu/arch_init.h
@@ -25,6 +25,7 @@ enum {
QEMU_ARCH_NIOS2 = (1 << 17),
QEMU_ARCH_HPPA = (1 << 18),
QEMU_ARCH_RISCV = (1 << 19),
+ QEMU_ARCH_RX = (1 << 20),
};
extern const uint32_t arch_type;
--
2.11.0
- [Qemu-devel] [PATCH v11 00/12] Add RX archtecture support, Yoshinori Sato, 2019/05/13
- [Qemu-devel] [PATCH v11 12/12] MAINTAINERS: Add RX, Yoshinori Sato, 2019/05/13
- [Qemu-devel] [PATCH v11 02/12] target/rx: TCG helper, Yoshinori Sato, 2019/05/13
- [Qemu-devel] [PATCH v11 04/12] target/rx: RX disassembler, Yoshinori Sato, 2019/05/13
- [Qemu-devel] [PATCH v11 01/12] target/rx: TCG translation, Yoshinori Sato, 2019/05/13
- [Qemu-devel] [PATCH v11 05/12] hw/intc: RX62N interrupt controller (ICUa), Yoshinori Sato, 2019/05/13
- [Qemu-devel] [PATCH v11 09/12] hw/registerfields.h: Add 8bit and 16bit register macros., Yoshinori Sato, 2019/05/13
- [Qemu-devel] [PATCH v11 10/12] qemu/bitops.h: Add extract8 and extract16, Yoshinori Sato, 2019/05/13
- [Qemu-devel] [PATCH v11 11/12] Add rx-softmmu,
Yoshinori Sato <=
- [Qemu-devel] [PATCH v11 07/12] hw/char: RX62N serial communication interface (SCI), Yoshinori Sato, 2019/05/13
- [Qemu-devel] [PATCH v11 08/12] hw/rx: RX Target hardware definition, Yoshinori Sato, 2019/05/13
- [Qemu-devel] [PATCH v11 03/12] target/rx: CPU definition, Yoshinori Sato, 2019/05/13
- [Qemu-devel] [PATCH v11 06/12] hw/timer: RX62N internal timer modules, Yoshinori Sato, 2019/05/13
- Re: [Qemu-devel] [PATCH v11 00/12] Add RX archtecture support, Philippe Mathieu-Daudé, 2019/05/13