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[Qemu-devel] [PULL 29/31] target/tricore: Use tcg_gen_abs_tl
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 29/31] target/tricore: Use tcg_gen_abs_tl |
Date: |
Mon, 13 May 2019 17:05:38 -0700 |
From: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/tricore/translate.c | 27 +++++----------------------
1 file changed, 5 insertions(+), 22 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 8f6416144e..06c4485e55 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -2415,11 +2415,7 @@ gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3,
uint32_t n, uint32_t mode)
static inline void gen_abs(TCGv ret, TCGv r1)
{
- TCGv temp = tcg_temp_new();
- TCGv t0 = tcg_const_i32(0);
-
- tcg_gen_neg_tl(temp, r1);
- tcg_gen_movcond_tl(TCG_COND_GE, ret, r1, t0, r1, temp);
+ tcg_gen_abs_tl(ret, r1);
/* overflow can only happen, if r1 = 0x80000000 */
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
@@ -2430,9 +2426,6 @@ static inline void gen_abs(TCGv ret, TCGv r1)
tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
/* calc SAV bit */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
-
- tcg_temp_free(temp);
- tcg_temp_free(t0);
}
static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
@@ -6617,13 +6610,8 @@ static void decode_rr_divide(CPUTriCoreState *env,
DisasContext *ctx)
tcg_gen_movi_tl(cpu_PSW_AV, 0);
if (!tricore_feature(env, TRICORE_FEATURE_131)) {
/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
- tcg_gen_neg_tl(temp, temp3);
- /* use cpu_PSW_AV to compare against 0 */
- tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
- temp, temp3);
- tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
- tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
- temp2, cpu_gpr_d[r2]);
+ tcg_gen_abs_tl(temp, temp3);
+ tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
} else {
/* overflow = (D[b] == 0) */
@@ -6655,13 +6643,8 @@ static void decode_rr_divide(CPUTriCoreState *env,
DisasContext *ctx)
tcg_gen_movi_tl(cpu_PSW_AV, 0);
if (!tricore_feature(env, TRICORE_FEATURE_131)) {
/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
- tcg_gen_neg_tl(temp, temp3);
- /* use cpu_PSW_AV to compare against 0 */
- tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
- temp, temp3);
- tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
- tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
- temp2, cpu_gpr_d[r2]);
+ tcg_gen_abs_tl(temp, temp3);
+ tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
} else {
/* overflow = (D[b] == 0) */
--
2.17.1
- [Qemu-devel] [PULL 00/31] tcg: gvec improvments, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 07/31] tcg: Return bool success from tcg_out_mov, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 13/31] tcg/aarch64: Implement tcg_out_dupm_vec, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 12/31] tcg/i386: Implement tcg_out_dupm_vec, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 19/31] tcg/i386: Support vector scalar shift opcodes, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 02/31] tcg: Do not recreate INDEX_op_neg_vec unless supported, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 10/31] tcg: Manually expand INDEX_op_dup_vec, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 29/31] target/tricore: Use tcg_gen_abs_tl,
Richard Henderson <=
- [Qemu-devel] [PULL 21/31] tcg: Add support for vector absolute value, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 09/31] tcg: Promote tcg_out_{dup, dupi}_vec to backend interface, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 22/31] tcg/i386: Support vector absolute value, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 31/31] tcg/aarch64: Do not advertise minmax for MO_64, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 27/31] target/ppc: Use tcg_gen_abs_tl, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 24/31] target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 15/31] tcg: Add gvec expanders for variable shift, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 05/31] tcg: Assert fixed_reg is read-only, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 25/31] target/cris: Use tcg_gen_abs_tl, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 14/31] tcg: Add INDEX_op_dupm_vec, Richard Henderson, 2019/05/13