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[Qemu-devel] [PATCH 7/9] target/xtensa: implement block prefetch option
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH 7/9] target/xtensa: implement block prefetch option opcodes |
Date: |
Tue, 14 May 2019 13:44:45 -0700 |
Block prefetch option adds a bunch of non-privileged opcodes that may be
implemented as nops since QEMU doesn't model caches.
Signed-off-by: Max Filippov <address@hidden>
---
target/xtensa/translate.c | 42 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 24eb70d619d5..356eb9948701 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -3078,6 +3078,9 @@ static const XtensaOpcodeOps core_ops[] = {
.translate = translate_dcache,
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
+ .name = "dhi.b",
+ .translate = translate_nop,
+ }, {
.name = "dhu",
.translate = translate_dcache,
.op_flags = XTENSA_OP_PRIVILEGED,
@@ -3085,9 +3088,15 @@ static const XtensaOpcodeOps core_ops[] = {
.name = "dhwb",
.translate = translate_dcache,
}, {
+ .name = "dhwb.b",
+ .translate = translate_nop,
+ }, {
.name = "dhwbi",
.translate = translate_dcache,
}, {
+ .name = "dhwbi.b",
+ .translate = translate_nop,
+ }, {
.name = "dii",
.translate = translate_nop,
.op_flags = XTENSA_OP_PRIVILEGED,
@@ -3112,15 +3121,33 @@ static const XtensaOpcodeOps core_ops[] = {
.translate = translate_dcache,
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
+ .name = "dpfm.b",
+ .translate = translate_nop,
+ }, {
+ .name = "dpfm.bf",
+ .translate = translate_nop,
+ }, {
.name = "dpfr",
.translate = translate_nop,
}, {
+ .name = "dpfr.b",
+ .translate = translate_nop,
+ }, {
+ .name = "dpfr.bf",
+ .translate = translate_nop,
+ }, {
.name = "dpfro",
.translate = translate_nop,
}, {
.name = "dpfw",
.translate = translate_nop,
}, {
+ .name = "dpfw.b",
+ .translate = translate_nop,
+ }, {
+ .name = "dpfw.bf",
+ .translate = translate_nop,
+ }, {
.name = "dpfwo",
.translate = translate_nop,
}, {
@@ -3628,6 +3655,21 @@ static const XtensaOpcodeOps core_ops[] = {
.par = (const uint32_t[]){true},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
+ .name = "pfend.a",
+ .translate = translate_nop,
+ }, {
+ .name = "pfend.o",
+ .translate = translate_nop,
+ }, {
+ .name = "pfnxt.f",
+ .translate = translate_nop,
+ }, {
+ .name = "pfwait.a",
+ .translate = translate_nop,
+ }, {
+ .name = "pfwait.o",
+ .translate = translate_nop,
+ }, {
.name = "pitlb",
.translate = translate_ptlb,
.par = (const uint32_t[]){false},
--
2.11.0
- [Qemu-devel] [PATCH 0/9] target/xtensa: implement options for modern cores, Max Filippov, 2019/05/14
- [Qemu-devel] [PATCH 3/9] target/xtensa: define IDMA and gather/scatter IRQ types, Max Filippov, 2019/05/14
- [Qemu-devel] [PATCH 8/9] target/xtensa: update list of exception causes, Max Filippov, 2019/05/14
- [Qemu-devel] [PATCH 7/9] target/xtensa: implement block prefetch option opcodes,
Max Filippov <=
- [Qemu-devel] [PATCH 9/9] target/xtensa: implement exclusive access option, Max Filippov, 2019/05/14
- [Qemu-devel] [PATCH 6/9] target/xtensa: implement DIWBUI.P opcode, Max Filippov, 2019/05/14
- [Qemu-devel] [PATCH 4/9] target/xtensa: add parity/ECC option SRs, Max Filippov, 2019/05/14
- [Qemu-devel] [PATCH 5/9] target/xtensa: implement MPU option, Max Filippov, 2019/05/14
- [Qemu-devel] [PATCH 2/9] target/xtensa: make internal MMU functions static, Max Filippov, 2019/05/14
- [Qemu-devel] [PATCH 1/9] target/xtensa: get rid of centralized SR properties, Max Filippov, 2019/05/14