[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v13 10/12] hw/registerfields.h: Add 8bit and 16bit r
From: |
Yoshinori Sato |
Subject: |
[Qemu-devel] [PATCH v13 10/12] hw/registerfields.h: Add 8bit and 16bit register macros. |
Date: |
Thu, 16 May 2019 14:52:42 +0900 |
Some RX peripheral using 8bit and 16bit registers.
Added 8bit and 16bit APIs.
Signed-off-by: Yoshinori Sato <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
include/hw/registerfields.h | 32 +++++++++++++++++++++++++++++++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
index 2659a58737..a0bb0654d6 100644
--- a/include/hw/registerfields.h
+++ b/include/hw/registerfields.h
@@ -22,6 +22,14 @@
enum { A_ ## reg = (addr) }; \
enum { R_ ## reg = (addr) / 4 };
+#define REG8(reg, addr) \
+ enum { A_ ## reg = (addr) }; \
+ enum { R_ ## reg = (addr) };
+
+#define REG16(reg, addr) \
+ enum { A_ ## reg = (addr) }; \
+ enum { R_ ## reg = (addr) / 2 };
+
/* Define SHIFT, LENGTH and MASK constants for a field within a register */
/* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH
@@ -34,6 +42,12 @@
MAKE_64BIT_MASK(shift, length)};
/* Extract a field from a register */
+#define FIELD_EX8(storage, reg, field) \
+ extract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH)
+#define FIELD_EX16(storage, reg, field) \
+ extract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH)
#define FIELD_EX32(storage, reg, field) \
extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
R_ ## reg ## _ ## field ## _LENGTH)
@@ -49,6 +63,22 @@
* Assigning values larger then the target field will result in
* compilation warnings.
*/
+#define FIELD_DP8(storage, reg, field, val) ({ \
+ struct { \
+ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
+ } v = { .v = val }; \
+ uint8_t d; \
+ d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH, v.v); \
+ d; })
+#define FIELD_DP16(storage, reg, field, val) ({ \
+ struct { \
+ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
+ } v = { .v = val }; \
+ uint16_t d; \
+ d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH, v.v); \
+ d; })
#define FIELD_DP32(storage, reg, field, val) ({ \
struct { \
unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
@@ -57,7 +87,7 @@
d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
R_ ## reg ## _ ## field ## _LENGTH, v.v); \
d; })
-#define FIELD_DP64(storage, reg, field, val) ({ \
+#define FIELD_DP64(storage, reg, field, val) ({ \
struct { \
unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
} v = { .v = val }; \
--
2.11.0
- [Qemu-devel] [PATCH v13 00/12] Add RX archtecture support, Yoshinori Sato, 2019/05/16
- [Qemu-devel] [PATCH v13 09/12] Add rx-softmmu, Yoshinori Sato, 2019/05/16
- [Qemu-devel] [PATCH v13 05/12] hw/intc: RX62N interrupt controller (ICUa), Yoshinori Sato, 2019/05/16
- [Qemu-devel] [PATCH v13 10/12] hw/registerfields.h: Add 8bit and 16bit register macros.,
Yoshinori Sato <=
- [Qemu-devel] [PATCH v13 08/12] hw/rx: RX Target hardware definition, Yoshinori Sato, 2019/05/16
- [Qemu-devel] [PATCH v13 11/12] qemu/bitops.h: Add extract8 and extract16, Yoshinori Sato, 2019/05/16
- [Qemu-devel] [PATCH v13 02/12] target/rx: TCG helper, Yoshinori Sato, 2019/05/16
- [Qemu-devel] [PATCH v13 03/12] target/rx: CPU definition, Yoshinori Sato, 2019/05/16
- [Qemu-devel] [PATCH v13 12/12] MAINTAINERS: Add RX, Yoshinori Sato, 2019/05/16
- [Qemu-devel] [PATCH v13 04/12] target/rx: RX disassembler, Yoshinori Sato, 2019/05/16