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[Qemu-devel] [RFC v1 09/23] target/riscv: Add Hypervisor CSR access func
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [RFC v1 09/23] target/riscv: Add Hypervisor CSR access functions |
Date: |
Fri, 24 May 2019 16:45:58 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/csr.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index c1fcb795cd..c52fde6e7f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -82,6 +82,20 @@ static int smode(CPURISCVState *env, int csrno)
return -!riscv_has_ext(env, RVS);
}
+static int hmode(CPURISCVState *env, int csrno)
+{
+ if (riscv_has_ext(env, RVS) &&
+ riscv_has_ext(env, RVH)) {
+ /* Hypervisor extension is supported */
+ if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+ env->priv == PRV_M) {
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
static int pmp(CPURISCVState *env, int csrno)
{
return -!riscv_feature(env, RISCV_FEATURE_PMP);
@@ -727,6 +741,55 @@ static int write_satp(CPURISCVState *env, int csrno,
target_ulong val)
return 0;
}
+/* Hypervisor Extensions */
+static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->hstatus;
+ return 0;
+}
+
+static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->hstatus = val;
+ return 0;
+}
+
+static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->hedeleg;
+ return 0;
+}
+
+static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->hedeleg = val;
+ return 0;
+}
+
+static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->hideleg;
+ return 0;
+}
+
+static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->hideleg = val;
+ return 0;
+}
+
+static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->hgatp;
+ return 0;
+}
+
+static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->hgatp = val;
+ return 0;
+}
+
/* Physical Memory Protection */
static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
{
@@ -910,6 +973,11 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Supervisor Protection and Translation */
[CSR_SATP] = { smode, read_satp, write_satp },
+ [CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus
},
+ [CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg
},
+ [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg
},
+ [CSR_HGATP] = { hmode, read_hgatp, write_hgatp
},
+
/* Physical Memory Protection */
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
--
2.21.0
- [Qemu-devel] [RFC v1 14/23] riscv: plic: Remove unused interrupt functions, (continued)
- [Qemu-devel] [RFC v1 14/23] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 17/23] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 16/23] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 12/23] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 13/23] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 06/23] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 11/23] target/riscv: Add background register swapping function, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 08/23] target/riscv: Add support for background interrupt setting, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 03/23] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 01/23] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 09/23] target/riscv: Add Hypervisor CSR access functions,
Alistair Francis <=
- [Qemu-devel] [RFC v1 10/23] target/riscv: Add background CSRs accesses, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 07/23] target/riscv: Remove strict perm checking for CSR R/W, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 05/23] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 04/23] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/05/24
- [Qemu-devel] [RFC v1 02/23] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/05/24