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Re: [Qemu-devel] [PATCH RFC v20 5/8] target/avr: Add instruction transla
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH RFC v20 5/8] target/avr: Add instruction translation |
Date: |
Fri, 31 May 2019 10:31:27 -0500 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 |
On 5/30/19 2:07 PM, Michael Rolnik wrote:
> + /* decode first instruction */
> + ctx.inst[0].cpc = pc_start;
> + decode_opc(&ctx, &ctx.inst[0]);
> + do {
> + /* set curr/next PCs */
> + cpc = ctx.inst[0].cpc;
> + npc = ctx.inst[0].npc;
> +
> + /* decode next instruction */
> + ctx.inst[1].cpc = ctx.inst[0].npc;
> + decode_opc(&ctx, &ctx.inst[1]);
> +
> + /* translate current instruction */
> + tcg_gen_insn_start(cpc);
> + num_insns++;
I don't believe that this simultaneous decode of two instructions is correct.
Consider if ctx.inst[0] is a branch instruction that is placed as the very last
word of memory. Ordinarily, the branch would be executed and the
TranslationBlock ended.
However, the advance read of ctx.inst[1] will cause a read from unmapped
address space (causing an exception), or read from a device (causing "Bad ram
pointer" and an abort from qemu_ram_addr_from_host_nofail).
I believe that the feature that you're attempting to support with this, skip
the next instruction, should be handled via an internal flag bit. This would
end up looking a lot like the HPPA nullify bit, or somewhat like the ARM thumb
condexec_mask. I can go into specifics if needed.
Such a change would also allow you to structure this code to use
"exec/translator.h", which in the future will likely be mandatory.
r~
- [Qemu-devel] [PATCH RFC v20 1/8] target/avr: Add outward facing interfaces and core CPU logic, (continued)
- [Qemu-devel] [PATCH RFC v20 7/8] target/avr: Add example board configuration, Michael Rolnik, 2019/05/30
- [Qemu-devel] [PATCH RFC v20 8/8] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file, Michael Rolnik, 2019/05/30
- [Qemu-devel] [PATCH RFC v20 6/8] target/avr: Add limited support for USART and 16 bit timer peripherals, Michael Rolnik, 2019/05/30
- [Qemu-devel] [PATCH RFC v20 5/8] target/avr: Add instruction translation, Michael Rolnik, 2019/05/30
- Re: [Qemu-devel] [PATCH RFC v20 5/8] target/avr: Add instruction translation,
Richard Henderson <=
- Re: [Qemu-devel] [PATCH RFC v20 0/8] QEMU AVR 8 bit cores, no-reply, 2019/05/30