Re: [Qemu-devel] [PATCH 8/8] target/ppc: Refactor emulation of vmrgew and vmrgow instructions

[Richard Henderson]

On 6/6/19 5:15 AM, Stefan Brankovic wrote:
> +/*
> + * We use this macro if one instruction is realized with direct
> + * translation, and second one with helper.
> + */
> +#define GEN_VXFORM_TRANS_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)\
> +static void glue(gen_, name0##_##name1)(DisasContext *ctx)             \
> +{                                                                      \
> +    if ((Rc(ctx->opcode) == 0) &&                                      \
> +        ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
> +        trans_##name0(ctx);                                            \
> +    } else if ((Rc(ctx->opcode) == 1) &&                               \
> +        ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
> +        gen_##name1(ctx);                                              \
> +    } else {                                                           \
> +        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);            \
> +    }                                                                  \
> +}
> +
>  /* Adds support to provide invalid mask */
>  #define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0,                \
>                              name1, flg1, flg2_1, inval1)                \
> @@ -431,20 +449,13 @@ GEN_VXFORM(vmrglb, 6, 4);
>  GEN_VXFORM(vmrglh, 6, 5);
>  GEN_VXFORM(vmrglw, 6, 6);
>  
> -static void gen_vmrgew(DisasContext *ctx)
> +static void trans_vmrgew(DisasContext *ctx)
>  {
> -    TCGv_i64 tmp;
> -    TCGv_i64 avr;
> -    int VT, VA, VB;
> -    if (unlikely(!ctx->altivec_enabled)) {
> -        gen_exception(ctx, POWERPC_EXCP_VPU);
> -        return;
> -    }

This appears to drop the check for altivec_enabled.


r~