Re: [Qemu-devel] [PATCH v2 2/2] hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1

[Peter Maydell]

Ping for code review, please?

thanks
-- PMM

On Fri, 24 May 2019 at 13:42, Peter Maydell <address@hidden> wrote:
>
> The GICv3 specification says that the GICD_TYPER.SecurityExtn bit
> is RAZ if GICD_CTLR.DS is 1. We were incorrectly making it RAZ
> if the security extension is unsupported. "Security extension
> unsupported" always implies GICD_CTLR.DS == 1, but the guest can
> also set DS on a GIC which does support the security extension.
> Fix the condition to correctly check the GICD_CTLR.DS bit.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
>  hw/intc/arm_gicv3_dist.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
> index e6fe4905fd3..b65f56f9035 100644
> --- a/hw/intc/arm_gicv3_dist.c
> +++ b/hw/intc/arm_gicv3_dist.c
> @@ -378,8 +378,14 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr 
> offset,
>           * ITLinesNumber == (num external irqs / 32) - 1
>           */
>          int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1;
> +        /*
> +         * SecurityExtn must be RAZ if GICD_CTLR.DS == 1, and
> +         * "security extensions not supported" always implies DS == 1,
> +         * so we only need to check the DS bit.
> +         */
> +        bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS);
>
> -        *data = (1 << 25) | (1 << 24) | (s->security_extn << 10) |
> +        *data = (1 << 25) | (1 << 24) | (sec_extn << 10) |
>              (0xf << 19) | itlinesnumber;
>          return MEMTX_OK;
>      }
> --
> 2.20.1
>