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[Qemu-devel] [PULL 02/13] target/ppc: Fix lxvw4x, lxvh8x and lxvb16x
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 02/13] target/ppc: Fix lxvw4x, lxvh8x and lxvb16x |
Date: |
Wed, 12 Jun 2019 15:49:18 +1000 |
From: Anton Blanchard <address@hidden>
During the conversion these instructions were incorrectly treated as
stores. We need to use set_cpu_vsr* and not get_cpu_vsr*.
Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}()
helpers for VSR register access")
Signed-off-by: Anton Blanchard <address@hidden>
Reviewed-by: Mark Cave-Ayland <address@hidden>
Tested-by: Greg Kurz <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate/vsx-impl.inc.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 199d22da97..cdb44b8b70 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -102,8 +102,7 @@ static void gen_lxvw4x(DisasContext *ctx)
}
xth = tcg_temp_new_i64();
xtl = tcg_temp_new_i64();
- get_cpu_vsrh(xth, xT(ctx->opcode));
- get_cpu_vsrl(xtl, xT(ctx->opcode));
+
gen_set_access_type(ctx, ACCESS_INT);
EA = tcg_temp_new();
@@ -126,6 +125,8 @@ static void gen_lxvw4x(DisasContext *ctx)
tcg_gen_addi_tl(EA, EA, 8);
tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);
}
+ set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsrl(xT(ctx->opcode), xtl);
tcg_temp_free(EA);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -185,8 +186,6 @@ static void gen_lxvh8x(DisasContext *ctx)
}
xth = tcg_temp_new_i64();
xtl = tcg_temp_new_i64();
- get_cpu_vsrh(xth, xT(ctx->opcode));
- get_cpu_vsrl(xtl, xT(ctx->opcode));
gen_set_access_type(ctx, ACCESS_INT);
EA = tcg_temp_new();
@@ -197,6 +196,8 @@ static void gen_lxvh8x(DisasContext *ctx)
if (ctx->le_mode) {
gen_bswap16x8(xth, xtl, xth, xtl);
}
+ set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsrl(xT(ctx->opcode), xtl);
tcg_temp_free(EA);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -214,14 +215,14 @@ static void gen_lxvb16x(DisasContext *ctx)
}
xth = tcg_temp_new_i64();
xtl = tcg_temp_new_i64();
- get_cpu_vsrh(xth, xT(ctx->opcode));
- get_cpu_vsrl(xtl, xT(ctx->opcode));
gen_set_access_type(ctx, ACCESS_INT);
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ);
tcg_gen_addi_tl(EA, EA, 8);
tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);
+ set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsrl(xT(ctx->opcode), xtl);
tcg_temp_free(EA);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
--
2.21.0
- [Qemu-devel] [PULL 00/13] ppc-for-4.1 queue 20190612, David Gibson, 2019/06/12
- [Qemu-devel] [PULL 03/13] spapr: Clean up device node name generation for PCI devices, David Gibson, 2019/06/12
- [Qemu-devel] [PULL 02/13] target/ppc: Fix lxvw4x, lxvh8x and lxvb16x,
David Gibson <=
- [Qemu-devel] [PULL 01/13] spapr_pci: Improve error message, David Gibson, 2019/06/12
- [Qemu-devel] [PULL 09/13] spapr: Direct all PCI hotplug to host bridge, rather than P2P bridge, David Gibson, 2019/06/12
- [Qemu-devel] [PULL 04/13] spapr: Clean up device tree construction for PCI devices, David Gibson, 2019/06/12
- [Qemu-devel] [PULL 12/13] ppc/pnv: activate the "dumpdtb" option on the powernv machine, David Gibson, 2019/06/12
- [Qemu-devel] [PULL 08/13] spapr: Don't use bus number for building DRC ids, David Gibson, 2019/06/12
- [Qemu-devel] [PULL 13/13] ppc/xive: Make XIVE generate the proper interrupt types, David Gibson, 2019/06/12
- [Qemu-devel] [PULL 10/13] spapr: Allow hot plug/unplug of PCI bridges and devices under PCI bridges, David Gibson, 2019/06/12
- [Qemu-devel] [PULL 07/13] spapr: Clean up DRC index construction, David Gibson, 2019/06/12
- [Qemu-devel] [PULL 06/13] spapr: Clean up spapr_drc_populate_dt(), David Gibson, 2019/06/12
- [Qemu-devel] [PULL 05/13] spapr: Clean up dt creation for PCI buses, David Gibson, 2019/06/12