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[Qemu-devel] [PULL 10/48] target/arm: Fix Cortex-R5F MVFR values
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/48] target/arm: Fix Cortex-R5F MVFR values |
Date: |
Thu, 13 Jun 2019 13:13:55 +0100 |
The Cortex-R5F initfn was not correctly setting up the MVFR
ID register values. Fill these in, since some subsequent patches
will use ID register checks rather than CPU feature bit checks.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/arm/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 4d5d46db7f0..c8441fc07b7 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1609,6 +1609,8 @@ static void cortex_r5f_initfn(Object *obj)
cortex_r5_initfn(obj);
set_feature(&cpu->env, ARM_FEATURE_VFP3);
+ cpu->isar.mvfr0 = 0x10110221;
+ cpu->isar.mvfr1 = 0x00000011;
}
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
--
2.20.1
- [Qemu-devel] [PULL 00/48] target-arm queue, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 01/48] target/arm: Vectorize USHL and SSHL, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 02/48] target/arm: Use tcg_gen_gvec_bitsel, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 06/48] target/arm: Fix output of PAuth Auth, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 07/48] decodetree: Fix comparison of Field, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 12/48] target/arm: Convert the VSEL instructions to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 11/48] target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 08/48] target/arm: Add stubs for AArch32 VFP decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 10/48] target/arm: Fix Cortex-R5F MVFR values,
Peter Maydell <=
- [Qemu-devel] [PULL 20/48] target/arm: Convert VFP two-register transfer insns to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 05/48] hw/core/bus.c: Only the main system bus can have no parent, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 19/48] target/arm: Convert "single-precision" register moves to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 21/48] target/arm: Convert VFP VLDR and VSTR to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 04/48] hw/arm/smmuv3: Fix decoding of ID register range, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 03/48] target/arm: Implement NSACR gating of floating point, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 18/48] target/arm: Convert "double-precision" register moves to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 15/48] target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 28/48] target/arm: Convert VMUL to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 30/48] target/arm: Convert VADD to decodetree, Peter Maydell, 2019/06/13