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[Qemu-devel] [PULL 27/48] target/arm: Convert VFP VNMLA to decodetree
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 27/48] target/arm: Convert VFP VNMLA to decodetree |
Date: |
Thu, 13 Jun 2019 13:14:12 +0100 |
Convert the VFP VNMLA instruction to decodetree.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/arm/translate-vfp.inc.c | 34 ++++++++++++++++++++++++++++++++++
target/arm/translate.c | 19 +------------------
target/arm/vfp.decode | 5 +++++
3 files changed, 40 insertions(+), 18 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 1d7100debe4..8532bf4abcd 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -1383,3 +1383,37 @@ static bool trans_VNMLS_dp(DisasContext *s, arg_VNMLS_sp
*a)
{
return do_vfp_3op_dp(s, gen_VNMLS_dp, a->vd, a->vn, a->vm, true);
}
+
+static void gen_VNMLA_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
+{
+ /* VNMLA: -fd + -(fn * fm) */
+ TCGv_i32 tmp = tcg_temp_new_i32();
+
+ gen_helper_vfp_muls(tmp, vn, vm, fpst);
+ gen_helper_vfp_negs(tmp, tmp);
+ gen_helper_vfp_negs(vd, vd);
+ gen_helper_vfp_adds(vd, vd, tmp, fpst);
+ tcg_temp_free_i32(tmp);
+}
+
+static bool trans_VNMLA_sp(DisasContext *s, arg_VNMLA_sp *a)
+{
+ return do_vfp_3op_sp(s, gen_VNMLA_sp, a->vd, a->vn, a->vm, true);
+}
+
+static void gen_VNMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
+{
+ /* VNMLA: -fd + (fn * fm) */
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ gen_helper_vfp_muld(tmp, vn, vm, fpst);
+ gen_helper_vfp_negd(tmp, tmp);
+ gen_helper_vfp_negd(vd, vd);
+ gen_helper_vfp_addd(vd, vd, tmp, fpst);
+ tcg_temp_free_i64(tmp);
+}
+
+static bool trans_VNMLA_dp(DisasContext *s, arg_VNMLA_sp *a)
+{
+ return do_vfp_3op_dp(s, gen_VNMLA_dp, a->vd, a->vn, a->vm, true);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 42701884101..0b998552df2 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1393,16 +1393,6 @@ VFP_OP2(div)
#undef VFP_OP2
-static inline void gen_vfp_F1_neg(int dp)
-{
- /* Like gen_vfp_neg() but put result in F1 */
- if (dp) {
- gen_helper_vfp_negd(cpu_F1d, cpu_F0d);
- } else {
- gen_helper_vfp_negs(cpu_F1s, cpu_F0s);
- }
-}
-
static inline void gen_vfp_abs(int dp)
{
if (dp)
@@ -3122,7 +3112,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
rn = VFP_SREG_N(insn);
switch (op) {
- case 0 ... 2:
+ case 0 ... 3:
/* Already handled by decodetree */
return 1;
default:
@@ -3308,13 +3298,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
for (;;) {
/* Perform the calculation. */
switch (op) {
- case 3: /* VNMLA: -fd + -(fn * fm) */
- gen_vfp_mul(dp);
- gen_vfp_F1_neg(dp);
- gen_mov_F0_vreg(dp, rd);
- gen_vfp_neg(dp);
- gen_vfp_add(dp);
- break;
case 4: /* mul: fn * fm */
gen_vfp_mul(dp);
break;
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index 08e4f427408..c50d2c3ebf3 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -112,3 +112,8 @@ VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... \
vm=%vm_sp vn=%vn_sp vd=%vd_sp
VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp
+
+VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... \
+ vm=%vm_sp vn=%vn_sp vd=%vd_sp
+VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... \
+ vm=%vm_dp vn=%vn_dp vd=%vd_dp
--
2.20.1
- [Qemu-devel] [PULL 20/48] target/arm: Convert VFP two-register transfer insns to decodetree, (continued)
- [Qemu-devel] [PULL 20/48] target/arm: Convert VFP two-register transfer insns to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 05/48] hw/core/bus.c: Only the main system bus can have no parent, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 19/48] target/arm: Convert "single-precision" register moves to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 21/48] target/arm: Convert VFP VLDR and VSTR to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 04/48] hw/arm/smmuv3: Fix decoding of ID register range, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 03/48] target/arm: Implement NSACR gating of floating point, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 18/48] target/arm: Convert "double-precision" register moves to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 15/48] target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 28/48] target/arm: Convert VMUL to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 30/48] target/arm: Convert VADD to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 27/48] target/arm: Convert VFP VNMLA to decodetree,
Peter Maydell <=
- [Qemu-devel] [PULL 09/48] target/arm: Factor out VFP access checking code, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 25/48] target/arm: Convert VFP VMLS to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 31/48] target/arm: Convert VSUB to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 43/48] target/arm: Convert double-single precision conversion insns to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 42/48] target/arm: Convert VFP round insns to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 23/48] target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 45/48] target/arm: Convert VJCVT to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 47/48] target/arm: Convert float-to-integer VCVT insns to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 32/48] target/arm: Convert VDIV to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 35/48] target/arm: Convert VABS to decodetree, Peter Maydell, 2019/06/13