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[Qemu-devel] [PATCH v4 00/13] target/ppc, tcg, tcg/i386: Optimize emulat

From: Stefan Brankovic
Subject: [Qemu-devel] [PATCH v4 00/13] target/ppc, tcg, tcg/i386: Optimize emulation of some Altivec instructions
Date: Thu, 27 Jun 2019 12:56:12 +0200

Optimize emulation of ten Altivec instructions: lvsl, lvsr, vsl, vsr, vgbbd,
vclzb, vclzh, vclzw, vclzd, vmrghb, vmrghh, vmrghw, vmrglb, vmrglh and vmrglw.

This series buils up on and complements recent work of Thomas Murta, Mark
Cave-Ayland and Richard Henderson in the same area. It is based on devising TCG
translation implementation for selected instructions rather than using helpers.
The selected instructions are most of the time idiosyncratic to ppc platform,
so relatively complex TCG translation (without direct mapping to host
instruction that is not possible in these cases) seems to be the best option,
and that approach is presented in this series.

This series also adds opcodes for vector implementation of instructions 
vmrgh(b|h|w) and vmrgl(b|h|w) in tcg, alongside with vector implementation of
those instructions for i386 targets in tcg backend.

The performance improvements are significant in all cases.


Addressed Richard's Henderson's suggestions.
Removed vpkpx's optimization for further investigation on graphical distortions
it caused on OSX 10.2-4 guests.
Added opcodes for vector vmrgh(b|h|w) and vmrgl(b|h|w) in tcg.
Implemented vector vmrgh and vmrgl instructions for i386.
Converted vmrgh and vmrgl instructions to vector operations.


Fixed problem during build.


Addressed Richard's Henderson's suggestions.
Fixed problem during build on patch 2/8.
Rebased series to the latest qemu code.

Stefan Brankovic (13):
  target/ppc: Optimize emulation of lvsl and lvsr instructions
  target/ppc: Optimize emulation of vsl and vsr instructions
  target/ppc: Optimize emulation of vgbbd instruction
  target/ppc: Optimize emulation of vclzd instruction
  target/ppc: Optimize emulation of vclzw instruction
  target/ppc: Optimize emulation of vclzh and vclzb instructions
  target/ppc: Refactor emulation of vmrgew and vmrgow instructions
  tcg: Add opcodes for vector vmrgh instructions
  tcg/i386: Implement vector vmrgh instructions
  target/ppc: convert vmrgh instructions to vector operations
  tcg: Add opcodes for verctor vmrgl instructions
  tcg/i386: Implement vector vmrgl instructions
  target/ppc: convert vmrgl instructions to vector operations

 accel/tcg/tcg-runtime-gvec.c        |  84 ++++++
 accel/tcg/tcg-runtime.h             |   8 +
 target/ppc/helper.h                 |  15 -
 target/ppc/int_helper.c             | 353 -----------------------
 target/ppc/translate/vmx-impl.inc.c | 555 +++++++++++++++++++++++++++++++-----
 tcg/i386/tcg-target.h               |   2 +
 tcg/i386/tcg-target.inc.c           |  29 ++
 tcg/tcg-op-gvec.c                   |  47 +++
 tcg/tcg-op-gvec.h                   |   5 +
 tcg/tcg-op-vec.c                    |  10 +
 tcg/tcg-op.h                        |   3 +
 tcg/tcg-opc.h                       |   3 +
 tcg/tcg.c                           |   4 +
 tcg/tcg.h                           |   2 +
 14 files changed, 677 insertions(+), 443 deletions(-)


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