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[Qemu-devel] [PULL 22/32] RISC-V: Add support for the Zicsr extension
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PULL 22/32] RISC-V: Add support for the Zicsr extension |
Date: |
Wed, 3 Jul 2019 01:40:38 -0700 |
The various CSR instructions have been split out of the base ISA as part
of the ratification process. This patch adds a Zicsr argument, which
disables all the CSR instructions.
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/csr.c | 6 ++++++
3 files changed, 8 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index bbad39a337b3..915b9e77df33 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -442,6 +442,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+ DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ba551cd3082c..0adb307f3298 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -224,6 +224,7 @@ typedef struct RISCVCPU {
bool ext_u;
bool ext_counters;
bool ext_ifencei;
+ bool ext_icsr;
char *priv_spec;
char *user_spec;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index de67741f3648..e0d45867607a 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -793,6 +793,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong
*ret_value,
{
int ret;
target_ulong old_value;
+ RISCVCPU *cpu = env_archcpu(env);
/* check privileges and return -1 if check fails */
#if !defined(CONFIG_USER_ONLY)
@@ -803,6 +804,11 @@ int riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
}
#endif
+ /* ensure the CSR extension is enabled. */
+ if (!cpu->cfg.ext_icsr) {
+ return -1;
+ }
+
/* check predicate */
if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0)
{
return -1;
--
2.21.0
- [Qemu-devel] [PULL 20/32] target/riscv: Add support for disabling/enabling Counters, (continued)
- [Qemu-devel] [PULL 20/32] target/riscv: Add support for disabling/enabling Counters, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 19/32] target/riscv: Remove user version information, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 27/32] disas/riscv: Fix `rdinstreth` constraint, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 29/32] riscv: sifive_u: Update the plic hart config to support multicore, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 21/32] RISC-V: Add support for the Zifencei extension, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 25/32] riscv: virt: Add cpu-topology DT node., Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 24/32] RISC-V: Update syscall list for 32-bit support., Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 23/32] RISC-V: Clear load reservations on context switch and SC, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 32/32] hw/riscv: Extend the kernel loading support, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 30/32] hw/riscv: Split out the boot functions, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 22/32] RISC-V: Add support for the Zicsr extension,
Palmer Dabbelt <=
- [Qemu-devel] [PULL 28/32] riscv: sifive_u: Do not create hard-coded phandles in DT, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 31/32] hw/riscv: Add support for loading a firmware, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 26/32] disas/riscv: Disassemble reserved compressed encodings as illegal, Palmer Dabbelt, 2019/07/03
- Re: [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3, Peter Maydell, 2019/07/04