Re: [Qemu-devel] [RISU RFC PATCH v2 06/14] x86.risu: add MMX instructions

[Richard Henderson]

On 7/1/19 6:35 AM, Jan Bobek wrote:
> Add an x86 configuration file with all MMX instructions.
> 
> Signed-off-by: Jan Bobek <address@hidden>
> ---
>  x86.risu | 96 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 96 insertions(+)
>  create mode 100644 x86.risu

Note that most of these MMX instructions affect the FPU, not the vector unit.
We would want to extend risu again to handle this.  You'd also need to seed the
FPU with random data.

I was thinking for a moment that this is really beyond what you've signed up
for, but on second thoughts it's not.  Decoding SSE is really tangled with
decoding MMX, via the 0x66 prefix, and you'll want to be able to verify that
you don't regress.

> +# State Management Instructions
> +EMMS            MMX     00001111 01110111 !emit { }

I'm not sure this is really testable, because of the state change.  But we'll
see what happens with the aforementioned dumping.

> +# Arithmetic Instructions
> +PADDB           MMX     00001111 11111100 !emit { modrm(); mem(size => 8); }
> +PADDW           MMX     00001111 11111101 !emit { modrm(); mem(size => 8); }
> +PADDD           MMX     00001111 11111110 !emit { modrm(); mem(size => 8); }
> +PADDQ           MMX     00001111 11010100 !emit { modrm(); mem(size => 8); }

PADDQ is sse2.


r~