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Re: [Qemu-devel] [PULL 09/30] i.MX6UL: Add i.MX6UL SOC


From: Peter Maydell
Subject: Re: [Qemu-devel] [PULL 09/30] i.MX6UL: Add i.MX6UL SOC
Date: Thu, 11 Jul 2019 13:53:23 +0100

On Thu, 16 Aug 2018 at 14:47, Peter Maydell <address@hidden> wrote:
>
> From: Jean-Christophe Dubois <address@hidden>

> +enum FslIMX6ULConfiguration {
> +    FSL_IMX6UL_NUM_CPUS         = 1,

Hi; Coverity has just noticed some "unreachable code"
in places like the imx6ul realize function:

> +static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
> +{
> +    FslIMX6ULState *s = FSL_IMX6UL(dev);
> +    int i;
> +    qemu_irq irq;
> +    char name[NAME_SIZE];
> +
> +    if (smp_cpus > FSL_IMX6UL_NUM_CPUS) {
> +        error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
> +                   TYPE_FSL_IMX6UL, FSL_IMX6UL_NUM_CPUS, smp_cpus);
> +        return;
> +    }
> +
> +    for (i = 0; i < smp_cpus; i++) {
> +        Object *o = OBJECT(&s->cpu[i]);
> +
> +        object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC,
> +                                "psci-conduit", &error_abort);
> +
> +        /* On uniprocessor, the CBAR is set to 0 */
> +        if (smp_cpus > 1) {
> +            object_property_set_int(o, FSL_IMX6UL_A7MPCORE_ADDR,
> +                                    "reset-cbar", &error_abort);
> +        }

where here for instance, smp_cpus can never be > 1 because
there is only ever 1 CPU in an iMX6UL and we enforce that with
the smp_cpus > FSL_IMX6UL_NUM_CPUS check; so the call to
object_property_set_int() is dead unreachable code.

Is it the case that there really can only ever be 1 CPU
in these SoCs (in which case we might as well delete the
dead code), or are there future variants which have two
CPUs that we might want to model in future (in which case
the dead code has some purpose and we can just tell
Coverity to be quiet) ?

thanks
-- PMM



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