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[Qemu-devel] [RISU PATCH v3 04/18] risugen_x86_constraints: add module
From: |
Jan Bobek |
Subject: |
[Qemu-devel] [RISU PATCH v3 04/18] risugen_x86_constraints: add module |
Date: |
Thu, 11 Jul 2019 18:32:46 -0400 |
The module risugen_x86_constraints.pm provides environment for
evaluating x86 "!constraints" blocks. This is facilitated by the
single exported function eval_constraints_block.
Signed-off-by: Jan Bobek <address@hidden>
---
risugen_x86_constraints.pm | 154 +++++++++++++++++++++++++++++++++++++
1 file changed, 154 insertions(+)
create mode 100644 risugen_x86_constraints.pm
diff --git a/risugen_x86_constraints.pm b/risugen_x86_constraints.pm
new file mode 100644
index 0000000..a4ee687
--- /dev/null
+++ b/risugen_x86_constraints.pm
@@ -0,0 +1,154 @@
+#!/usr/bin/perl -w
+###############################################################################
+# Copyright (c) 2019 Jan Bobek
+# All rights reserved. This program and the accompanying materials
+# are made available under the terms of the Eclipse Public License v1.0
+# which accompanies this distribution, and is available at
+# http://www.eclipse.org/legal/epl-v10.html
+#
+# Contributors:
+# Jan Bobek - initial implementation
+###############################################################################
+
+# risugen_x86_constraints -- risugen_x86's helper module for "!constraints"
blocks
+package risugen_x86_constraints;
+
+use strict;
+use warnings;
+
+use risugen_common;
+use risugen_x86_asm;
+
+our @ISA = qw(Exporter);
+our @EXPORT = qw(eval_constraints_block);
+
+my $is_x86_64;
+
+sub data16($%)
+{
+ my ($insn, %data16) = @_;
+ $insn->{data16} = \%data16;
+}
+
+sub rep($%)
+{
+ my ($insn, %rep) = @_;
+ $insn->{rep} = \%rep;
+}
+
+sub repne($%)
+{
+ my ($insn, %repne) = @_;
+ $insn->{repne} = \%repne;
+}
+
+sub rex($%)
+{
+ my ($insn, %rex) = @_;
+ # It doesn't make sense to randomize any REX fields, since REX.W
+ # is opcode-like and REX.R/.X/.B are encoded automatically by
+ # risugen_x86_asm.
+ $insn->{rex} = \%rex;
+}
+
+sub vex($%)
+{
+ my ($insn, %vex) = @_;
+ my $regidw = $is_x86_64 ? 4 : 3;
+
+ # There is no point in randomizing other VEX fields, since
+ # VEX.R/.X/.B are encoded automatically by risugen_x86_asm, and
+ # VEX.M/.P are opcodes.
+ $vex{l} = randint(width => 1) ? 256 : 128 unless defined $vex{l};
+ $vex{v} = randint(width => $regidw) unless defined $vex{v};
+ $vex{w} = randint(width => 1) unless defined $vex{w};
+ $insn->{vex} = \%vex;
+}
+
+sub modrm_($%)
+{
+ my ($insn, %args) = @_;
+ my $regidw = $is_x86_64 ? 4 : 3;
+
+ my %modrm = ();
+ if (defined $args{reg}) {
+ # This makes the config file syntax a bit more accommodating
+ # in cases where MODRM.REG is an opcode extension field.
+ $modrm{reg} = $args{reg};
+ } else {
+ $modrm{reg} = randint(width => $regidw);
+ }
+
+ # There is also a displacement-only form, but we don't know
+ # absolute address of the memblock, so we cannot test it.
+ my $form = int(rand(4));
+ if ($form == 0) {
+ $modrm{reg2} = randint(width => $regidw);
+ } else {
+ $modrm{base} = randint(width => $regidw);
+
+ if ($form == 2) {
+ $modrm{base} = randint(width => $regidw);
+ $modrm{disp}{value} = randint(width => 8, signed => 1);
+ $modrm{disp}{width} = 8;
+ } elsif ($form == 3) {
+ $modrm{base} = randint(width => $regidw);
+ $modrm{disp}{value} = randint(width => 32, signed => 1);
+ $modrm{disp}{width} = 32;
+ }
+
+ my $have_index = int(rand(2));
+ if ($have_index) {
+ my $indexk = $args{indexk};
+ $modrm{ss} = randint(width => 2);
+ $modrm{$indexk} = randint(width => $regidw);
+ }
+ }
+
+ $insn->{modrm} = \%modrm;
+}
+
+sub modrm($%)
+{
+ my ($insn, %args) = @_;
+ modrm_($insn, indexk => 'index', %args);
+}
+
+sub modrm_vsib($%)
+{
+ my ($insn, %args) = @_;
+ modrm_($insn, indexk => 'vindex', %args);
+}
+
+sub imm($%)
+{
+ my ($insn, %args) = @_;
+ $insn->{imm}{value} = randint(%args);
+ $insn->{imm}{width} = $args{width};
+}
+
+sub eval_constraints_block(%)
+{
+ my (%args) = @_;
+ my $rec = $args{rec};
+ my $insn = $args{insn};
+ my $insnname = $rec->{name};
+ my $opcode = $insn->{opcode}{value};
+
+ $is_x86_64 = $args{is_x86_64};
+
+ my $constraint = $rec->{blocks}{"constraints"};
+ if (defined $constraint) {
+ # user-specified constraint: evaluate in an environment
+ # with variables set corresponding to the variable fields.
+ my %env = extract_fields($opcode, $rec);
+ # set the variable $_ to the instruction in question
+ $env{_} = $insn;
+
+ return eval_block($insnname, "constraints", $constraint, \%env);
+ } else {
+ return 1;
+ }
+}
+
+1;
--
2.20.1
- [Qemu-devel] [RISU PATCH v3 05/18] risugen_x86_memory: add module, (continued)
- [Qemu-devel] [RISU PATCH v3 05/18] risugen_x86_memory: add module, Jan Bobek, 2019/07/11
- [Qemu-devel] [RISU PATCH v3 11/18] x86.risu: add SSE instructions, Jan Bobek, 2019/07/11
- [Qemu-devel] [RISU PATCH v3 01/18] risugen_common: add helper functions insnv, randint, Jan Bobek, 2019/07/11
- [Qemu-devel] [RISU PATCH v3 07/18] risugen: allow all byte-aligned instructions, Jan Bobek, 2019/07/11
- [Qemu-devel] [RISU PATCH v3 02/18] risugen_common: split eval_with_fields into extract_fields and eval_block, Jan Bobek, 2019/07/11
- [Qemu-devel] [RISU PATCH v3 04/18] risugen_x86_constraints: add module,
Jan Bobek <=
- [Qemu-devel] [RISU PATCH v3 15/18] x86.risu: add SSE4.1 and SSE4.2 instructions, Jan Bobek, 2019/07/11
- [Qemu-devel] [RISU PATCH v3 03/18] risugen_x86_asm: add module, Jan Bobek, 2019/07/11
- [Qemu-devel] [RISU PATCH v3 14/18] x86.risu: add SSSE3 instructions, Jan Bobek, 2019/07/11