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[Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetr
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree |
Date: |
Fri, 26 Jul 2019 10:49:25 -0700 |
This unifies the implementation of the actual instructions
for a32, t32, and t16. In order to make this happen, we
need several preliminary cleanups. Most importantly to how
we handle the architectural representation of PC.
I attempt to convert single groups of instructions at once,
as they are grouped in the sections of the encoding sections
of the manual.
This has been tested by running the debian 9 armhf installer,
which does a far amount of switching between arm and thumb modes.
I've also run Peter's ARM TFM image, and all of the existing
RISU tests that we have. (Our RISU test cases are nowhere near
complete for 32-bit mode, but it did find 3 bugs, so not useless.)
What's left is converting NEON and iwmmxt, then we could start
merging some of the decoders and tidying the top-level interface
further.
We will need to convert NEON in order to have a good chance at
finishing the ARMv8.2-FHP extension.
r~
Richard Henderson (67):
decodetree: Allow !function with no input bits
target/arm: Remove offset argument to gen_exception_insn
target/arm: Remove offset argument to gen_exception_bkpt_insn
target/arm: Remove offset argument to gen_exception_internal_insn
target/arm: Use the saved value of the insn address
target/arm: Introduce pc_read
target/arm: Introduce add_reg_for_lit
target/arm: Use store_reg_from_load in thumb2 code
target/arm: Fold a pc load into load_reg
target/arm: Move test for AL into arm_skip_unless
target/arm: Add stubs for aa32 decodetree
target/arm: Introduce gen_illegal_op
target/arm: Convert Data Processing (reg, reg-shifted-reg, imm)
target/arm: Convert multiply and multiply accumulate
target/arm: Convert Saturating addition and subtraction
target/arm: Convert Halfword multiply and multiply accumulate
target/arm: Convert MSR (immediate) and hints
target/arm: Convert MRS/MSR (banked, register)
target/arm: Convert Cyclic Redundancy Check
target/arm: Convert the rest of A32 Miscelaneous instructions
target/arm: Convert T32 ADDW/SUBW
target/arm: Convert load/store (register, immediate, literal)
target/arm: Convert Synchronization primitives
target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF
target/arm: Convert Parallel addition and subtraction
target/arm: Convert Packing, unpacking, saturation, and reversal
target/arm: Convert Signed multiply, signed and unsigned divide
target/arm: Convert MOVW, MOVT
target/arm: Convert LDM, STM
target/arm: Convert B, BL, BLX (immediate)
target/arm: Convert SVC
target/arm: Convert RFE and SRS
target/arm: Convert Clear-Exclusive, Barriers
target/arm: Convert CPS (privileged)
target/arm: Convert SETEND
target/arm: Convert PLI, PLD, PLDW
target/arm: Convert Unallocated memory hint
target/arm: Convert Table Branch
target/arm: Convert SG
target/arm: Convert TT
target/arm: Simplify disas_thumb2_insn
target/arm: Simplify disas_arm_insn
target/arm: Add skeleton for T16 decodetree
target/arm: Convert T16 data-processing (two low regs)
target/arm: Convert T16 load/store (register offset)
target/arm: Convert T16 load/store (immediate offset)
target/arm: Convert T16 add pc/sp (immediate)
target/arm: Convert T16 load/store multiple
target/arm: Convert T16 add/sub (3 low, 2 low and imm)
target/arm: Convert T16 one low register and immediate
target/arm: Convert T16 branch and exchange
target/arm: Convert T16 add, compare, move (two high registers)
target/arm: Convert T16 adjust sp (immediate)
target/arm: Convert T16, extract
target/arm: Convert T16, Change processor state
target/arm: Convert T16, Reverse bytes
target/arm: Convert T16, nop hints
target/arm: Convert T16, push and pop
target/arm: Convert T16, Conditional branches, Supervisor call
target/arm: Convert T16, Miscellaneous 16-bit instructions
target/arm: Convert T16, shift immediate
target/arm: Convert T16, load (literal)
target/arm: Convert T16, Unconditional branch
target/arm: Convert T16, long branches
target/arm: Clean up disas_thumb_insn
target/arm: Move singlestep check from gen_jmp to gen_goto_tb
target/arm: Merge gen_bx_im into trans_BLX_i
target/arm/helper.h | 1 -
target/arm/translate.h | 10 +
target/arm/op_helper.c | 15 -
target/arm/translate-vfp.inc.c | 41 +-
target/arm/translate.c | 7142 ++++++++++++-----------------
scripts/decodetree.py | 5 +-
target/arm/Makefile.objs | 24 +
target/arm/a32-uncond.decode | 74 +
target/arm/a32.decode | 534 +++
target/arm/t16.decode | 279 ++
target/arm/t32.decode | 629 +++
tests/decode/succ_function.decode | 2 +
12 files changed, 4559 insertions(+), 4197 deletions(-)
create mode 100644 target/arm/a32-uncond.decode
create mode 100644 target/arm/a32.decode
create mode 100644 target/arm/t16.decode
create mode 100644 target/arm/t32.decode
create mode 100644 tests/decode/succ_function.decode
--
2.17.1
- [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree,
Richard Henderson <=