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[Qemu-devel] [PATCH 02/67] target/arm: Remove offset argument to gen_exc
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 02/67] target/arm: Remove offset argument to gen_exception_insn |
Date: |
Fri, 26 Jul 2019 10:49:27 -0700 |
The address of the current insn is still available in s->base.pc_next.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-vfp.inc.c | 6 +++---
target/arm/translate.c | 32 ++++++++++++++++----------------
2 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 092eb5ec53..e7389bc057 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -96,10 +96,10 @@ static bool full_vfp_access_check(DisasContext *s, bool
ignore_vfp_enabled)
{
if (s->fp_excp_el) {
if (arm_dc_feature(s, ARM_FEATURE_M)) {
- gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(),
+ gen_exception_insn(s, EXCP_NOCP, syn_uncategorized(),
s->fp_excp_el);
} else {
- gen_exception_insn(s, 4, EXCP_UDEF,
+ gen_exception_insn(s, EXCP_UDEF,
syn_fp_access_trap(1, 0xe, false),
s->fp_excp_el);
}
@@ -108,7 +108,7 @@ static bool full_vfp_access_check(DisasContext *s, bool
ignore_vfp_enabled)
if (!s->vfp_enabled && !ignore_vfp_enabled) {
assert(!arm_dc_feature(s, ARM_FEATURE_M));
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
+ gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
return false;
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7853462b21..33f78296eb 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1247,11 +1247,11 @@ static void gen_exception_internal_insn(DisasContext
*s, int offset, int excp)
s->base.is_jmp = DISAS_NORETURN;
}
-static void gen_exception_insn(DisasContext *s, int offset, int excp,
- int syn, uint32_t target_el)
+static void gen_exception_insn(DisasContext *s, int excp, int syn,
+ uint32_t target_el)
{
gen_set_condexec(s);
- gen_set_pc_im(s, s->pc - offset);
+ gen_set_pc_im(s, s->base.pc_next);
gen_exception(excp, syn, target_el);
s->base.is_jmp = DISAS_NORETURN;
}
@@ -1298,7 +1298,7 @@ static inline void gen_hlt(DisasContext *s, int imm)
return;
}
- gen_exception_insn(s, s->thumb ? 2 : 4, EXCP_UDEF, syn_uncategorized(),
+ gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
}
@@ -3175,7 +3175,7 @@ static bool msr_banked_access_decode(DisasContext *s, int
r, int sysm, int rn,
undef:
/* If we get here then some access check did not pass */
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), exc_target);
+ gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), exc_target);
return false;
}
@@ -3569,7 +3569,7 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t
insn)
* for attempts to execute invalid vfp/neon encodings with FP disabled.
*/
if (s->fp_excp_el) {
- gen_exception_insn(s, 4, EXCP_UDEF,
+ gen_exception_insn(s, EXCP_UDEF,
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
return 0;
}
@@ -4840,7 +4840,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t
insn)
* for attempts to execute invalid vfp/neon encodings with FP disabled.
*/
if (s->fp_excp_el) {
- gen_exception_insn(s, 4, EXCP_UDEF,
+ gen_exception_insn(s, EXCP_UDEF,
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
return 0;
}
@@ -6968,7 +6968,7 @@ static int disas_neon_insn_3same_ext(DisasContext *s,
uint32_t insn)
}
if (s->fp_excp_el) {
- gen_exception_insn(s, 4, EXCP_UDEF,
+ gen_exception_insn(s, EXCP_UDEF,
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
return 0;
}
@@ -7091,7 +7091,7 @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext
*s, uint32_t insn)
off_rm = vfp_reg_offset(0, rm);
}
if (s->fp_excp_el) {
- gen_exception_insn(s, 4, EXCP_UDEF,
+ gen_exception_insn(s, EXCP_UDEF,
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
return 0;
}
@@ -7584,7 +7584,7 @@ static void gen_srs(DisasContext *s,
* For the UNPREDICTABLE cases we choose to UNDEF.
*/
if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) {
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), 3);
+ gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), 3);
return;
}
@@ -7620,7 +7620,7 @@ static void gen_srs(DisasContext *s,
}
if (undef) {
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
+ gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
return;
}
@@ -7711,7 +7711,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int
insn)
* UsageFault exception.
*/
if (arm_dc_feature(s, ARM_FEATURE_M)) {
- gen_exception_insn(s, 4, EXCP_INVSTATE, syn_uncategorized(),
+ gen_exception_insn(s, EXCP_INVSTATE, syn_uncategorized(),
default_exception_el(s));
return;
}
@@ -9254,7 +9254,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int
insn)
break;
default:
illegal_op:
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
+ gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
break;
}
@@ -10288,7 +10288,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t
insn)
}
/* All other insns: NOCP */
- gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(),
+ gen_exception_insn(s, EXCP_NOCP, syn_uncategorized(),
default_exception_el(s));
break;
}
@@ -10972,7 +10972,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t
insn)
}
return;
illegal_op:
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
+ gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
}
@@ -11809,7 +11809,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
return;
illegal_op:
undef:
- gen_exception_insn(s, 2, EXCP_UDEF, syn_uncategorized(),
+ gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
}
--
2.17.1
- [Qemu-devel] [PATCH 03/67] target/arm: Remove offset argument to gen_exception_bkpt_insn, (continued)
- [Qemu-devel] [PATCH 03/67] target/arm: Remove offset argument to gen_exception_bkpt_insn, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 05/67] target/arm: Use the saved value of the insn address, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 04/67] target/arm: Remove offset argument to gen_exception_internal_insn, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 06/67] target/arm: Introduce pc_read, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 02/67] target/arm: Remove offset argument to gen_exception_insn,
Richard Henderson <=
- [Qemu-devel] [PATCH 07/67] target/arm: Introduce add_reg_for_lit, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 10/67] target/arm: Move test for AL into arm_skip_unless, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 08/67] target/arm: Use store_reg_from_load in thumb2 code, Richard Henderson, 2019/07/26