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[Qemu-devel] [PATCH 21/67] target/arm: Convert T32 ADDW/SUBW
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 21/67] target/arm: Convert T32 ADDW/SUBW |
Date: |
Fri, 26 Jul 2019 10:49:46 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 24 +++++++++++++-----------
target/arm/a32.decode | 1 +
target/arm/t32.decode | 19 +++++++++++++++++++
3 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 09310b1c3a..d19131d594 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7683,6 +7683,11 @@ static void arm_skip_unless(DisasContext *s, uint32_t
cond)
* Constant expanders for the decoders.
*/
+static int negate(DisasContext *s, int x)
+{
+ return -x;
+}
+
static int times_2(DisasContext *s, int x)
{
return x * 2;
@@ -8053,6 +8058,12 @@ static bool trans_ORN_rri(DisasContext *s, arg_s_rri_rot
*a)
#undef DO_ANY
#undef DO_LOGIC
+static bool trans_ADR(DisasContext *s, arg_ri *a)
+{
+ store_reg_bx(s, a->rd, add_reg_for_lit(s, 15, a->imm));
+ return true;
+}
+
/*
* Multiply and multiply accumulate
*/
@@ -10758,17 +10769,8 @@ static void disas_thumb2_insn(DisasContext *s,
uint32_t insn)
}
store_reg(s, rd, tmp);
} else {
- /* Add/sub 12-bit immediate. */
- if (insn & (1 << 23)) {
- imm = -imm;
- }
- tmp = add_reg_for_lit(s, rn, imm);
- if (rn == 13 && rd == 13) {
- /* ADD SP, SP, imm or SUB SP, SP, imm */
- store_sp_checked(s, tmp);
- } else {
- store_reg(s, rd, tmp);
- }
+ /* Add/sub 12-bit immediate, in decodetree */
+ goto illegal_op;
}
}
} else {
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 32d1833037..baae62dea9 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -30,6 +30,7 @@
&rrrr rd rn rm ra
&rrr rd rn rm
&rr rd rm
+&ri rd imm
&r rm
&i imm
&msr_reg rn r mask
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index abd233180d..69e81ef71a 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -27,6 +27,7 @@
&rrrr !extern rd rn rm ra
&rrr !extern rd rn rm
&rr !extern rd rm
+&ri !extern rd imm
&r !extern rm
&i !extern imm
&msr_reg !extern rn r mask
@@ -121,6 +122,24 @@ SBC_rri 1111 0.0 1011 . .... 0 ... .... ........
@s_rri_rot
}
RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot
+# Data processing (plain binary immediate)
+
+%imm12_26_12_0 26:1 12:3 0:8
+%neg12_26_12_0 26:1 12:3 0:8 !function=negate
+@s0_rri_12 .... ... .... . rn:4 . ... rd:4 ........ \
+ &s_rri_rot imm=%imm12_26_12_0 rot=0 s=0
+
+{
+ ADR 1111 0.1 0000 0 1111 0 ... rd:4 ........ \
+ &ri imm=%imm12_26_12_0
+ ADD_rri 1111 0.1 0000 0 .... 0 ... .... ........ @s0_rri_12
+}
+{
+ ADR 1111 0.1 0101 0 1111 0 ... rd:4 ........ \
+ &ri imm=%neg12_26_12_0
+ SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12
+}
+
# Multiply and multiply accumulate
@s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0
--
2.17.1
- [Qemu-devel] [PATCH 12/67] target/arm: Introduce gen_illegal_op, (continued)
- [Qemu-devel] [PATCH 12/67] target/arm: Introduce gen_illegal_op, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 09/67] target/arm: Fold a pc load into load_reg, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 15/67] target/arm: Convert Saturating addition and subtraction, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 16/67] target/arm: Convert Halfword multiply and multiply accumulate, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 14/67] target/arm: Convert multiply and multiply accumulate, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 20/67] target/arm: Convert the rest of A32 Miscelaneous instructions, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 18/67] target/arm: Convert MRS/MSR (banked, register), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 17/67] target/arm: Convert MSR (immediate) and hints, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 21/67] target/arm: Convert T32 ADDW/SUBW,
Richard Henderson <=
- [Qemu-devel] [PATCH 13/67] target/arm: Convert Data Processing (reg, reg-shifted-reg, imm), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 23/67] target/arm: Convert Synchronization primitives, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 25/67] target/arm: Convert Parallel addition and subtraction, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 24/67] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 19/67] target/arm: Convert Cyclic Redundancy Check, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 26/67] target/arm: Convert Packing, unpacking, saturation, and reversal, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 22/67] target/arm: Convert load/store (register, immediate, literal), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 27/67] target/arm: Convert Signed multiply, signed and unsigned divide, Richard Henderson, 2019/07/26