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[Qemu-devel] [PATCH 57/67] target/arm: Convert T16, nop hints
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 57/67] target/arm: Convert T16, nop hints |
Date: |
Fri, 26 Jul 2019 10:50:22 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 3 +--
target/arm/t16.decode | 17 +++++++++++++++++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index c9386ceefb..55404414a2 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10779,8 +10779,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
case 15: /* IT, nop-hint. */
if ((insn & 0xf) == 0) {
- gen_nop_hint(s, (insn >> 4) & 0xf);
- break;
+ goto illegal_op; /* nop hint, in decodetree */
}
/*
* IT (If-Then)
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 8864f89a81..90a4b71a45 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -19,6 +19,7 @@
# This file is processed by scripts/decodetree.py
#
+&empty !extern
&s_rrr_shi !extern s rd rn rm shim shty
&s_rrr_shr !extern s rn rd rm rs shty
&s_rri_rot !extern s rn rd imm rot
@@ -204,3 +205,19 @@ SETEND 1011 0110 010 1 E:1 000 &setend
REV 1011 1010 00 ... ... @rdm
REV16 1011 1010 01 ... ... @rdm
REVSH 1011 1010 11 ... ... @rdm
+
+# Hints
+
+{
+ YIELD 1011 1111 0001 0000
+ WFE 1011 1111 0010 0000
+ WFI 1011 1111 0011 0000
+
+ # TODO: Implement SEV, SEVL; may help SMP performance.
+ # SEV 1011 1111 0100 0000
+ # SEVL 1011 1111 0101 0000
+
+ # The canonical nop has the second nibble as 0000, but the whole of the
+ # rest of the space is a reserved hint, behaves as nop.
+ NOP 1011 1111 ---- 0000
+}
--
2.17.1
- [Qemu-devel] [PATCH 51/67] target/arm: Convert T16 branch and exchange, (continued)
- [Qemu-devel] [PATCH 51/67] target/arm: Convert T16 branch and exchange, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 41/67] target/arm: Simplify disas_thumb2_insn, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 53/67] target/arm: Convert T16 adjust sp (immediate), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 55/67] target/arm: Convert T16, Change processor state, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 61/67] target/arm: Convert T16, shift immediate, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 64/67] target/arm: Convert T16, long branches, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 67/67] target/arm: Merge gen_bx_im into trans_BLX_i, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 59/67] target/arm: Convert T16, Conditional branches, Supervisor call, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 58/67] target/arm: Convert T16, push and pop, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 57/67] target/arm: Convert T16, nop hints,
Richard Henderson <=
- [Qemu-devel] [PATCH 65/67] target/arm: Clean up disas_thumb_insn, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 56/67] target/arm: Convert T16, Reverse bytes, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 54/67] target/arm: Convert T16, extract, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 52/67] target/arm: Convert T16 add, compare, move (two high registers), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 63/67] target/arm: Convert T16, Unconditional branch, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 60/67] target/arm: Convert T16, Miscellaneous 16-bit instructions, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 62/67] target/arm: Convert T16, load (literal), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 66/67] target/arm: Move singlestep check from gen_jmp to gen_goto_tb, Richard Henderson, 2019/07/26