[Qemu-devel] [PATCH v3 16/18] ppc/pnv: Extend XivePresenter with a get_block_id() handler

[Cédric Le Goater]

When doing CAM line compares, fetch the block id from the interrupt
controller which can have set the PC_TCTXT_CHIPID field.

Signed-off-by: Cédric Le Goater <address@hidden>
---
 include/hw/ppc/xive.h | 1 +
 hw/intc/pnv_xive.c    | 6 ++++++
 hw/intc/spapr_xive.c  | 6 ++++++
 hw/intc/xive.c        | 8 +++++---
 4 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index e16c3b63fc44..d68fb6eea46e 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -391,6 +391,7 @@ typedef struct XivePresenterClass {
                      uint8_t nvt_blk, uint32_t nvt_idx,
                      bool cam_ignore, uint8_t priority,
                      uint32_t logic_serv, XiveTCTXMatch *match);
+    uint8_t (*get_block_id)(XivePresenter *xptr);
 } XivePresenterClass;
 
 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 6b7078aa4fde..8e3ba23788f7 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -460,6 +460,11 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t 
format,
     return count;
 }
 
+static uint8_t pnv_xive_get_block_id(XivePresenter *xptr)
+{
+    return pnv_xive_block_id(PNV_XIVE(xptr));
+}
+
 /*
  * The TIMA MMIO space is shared among the chips and to identify the
  * chip from which the access is being done, we extract the chip id
@@ -1918,6 +1923,7 @@ static void pnv_xive_class_init(ObjectClass *klass, void 
*data)
 
     xnc->notify = pnv_xive_notify;
     xpc->match_nvt  = pnv_xive_match_nvt;
+    xpc->get_block_id = pnv_xive_get_block_id;
 };
 
 static const TypeInfo pnv_xive_info = {
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 4abb099d341c..26fc815d3931 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -479,6 +479,11 @@ static int spapr_xive_match_nvt(XivePresenter *xptr, 
uint8_t format,
     return count;
 }
 
+static uint8_t spapr_xive_get_block_id(XivePresenter *xrtr)
+{
+    return SPAPR_XIVE_BLOCK_ID;
+}
+
 static const VMStateDescription vmstate_spapr_xive_end = {
     .name = TYPE_SPAPR_XIVE "/end",
     .version_id = 1,
@@ -570,6 +575,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void 
*data)
     xrc->write_nvt = spapr_xive_write_nvt;
 
     xpc->match_nvt  = spapr_xive_match_nvt;
+    xpc->get_block_id = spapr_xive_get_block_id;
 }
 
 static const TypeInfo spapr_xive_info = {
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 9b02ce423d66..e79439f6b940 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1305,12 +1305,14 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t 
nvt_blk, uint32_t nvt_idx,
  *
  *   chip << 19 | 0000000 0 0001 thread (7Bit)
  */
-static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx)
+static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx)
 {
     CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
     uint32_t pir = env->spr_cb[SPR_PIR].default_value;
+    XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
+    uint8_t blk = xpc->get_block_id(xptr);
 
-    return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f));
+    return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f));
 }
 
 /*
@@ -1347,7 +1349,7 @@ int xive_presenter_tctx_match(XivePresenter *xptr, 
XiveTCTX *tctx,
 
         /* PHYS ring */
         if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) &&
-            cam == xive_tctx_hw_cam_line(tctx)) {
+            cam == xive_tctx_hw_cam_line(xptr, tctx)) {
             return TM_QW3_HV_PHYS;
         }
 
-- 
2.21.0