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Re: [Qemu-devel] [PATCH v3 04/18] ppc/pnv: Implement the XiveFabric and
From: |
Cédric Le Goater |
Subject: |
Re: [Qemu-devel] [PATCH v3 04/18] ppc/pnv: Implement the XiveFabric and XivePresenter interfaces |
Date: |
Wed, 31 Jul 2019 16:21:47 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 |
On 31/07/2019 16:12, Cédric Le Goater wrote:
> The CAM line matching on the PowerNV machine now scans all chips of
> the system and all CPUs of a chip to find a dispatched NVT in the
> thread contexts.
>
> As there is now easy way to loop on the CPUs belonging to a chip, the
> PowerNV handler loops on all CPUs and filter out the external CPUs.
>
> Fixes: af53dbf6227a ("ppc/xive: introduce a simplified XIVE presenter")
> Signed-off-by: Cédric Le Goater <address@hidden>
> ---
> hw/intc/pnv_xive.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++
> hw/ppc/pnv.c | 32 +++++++++++++++++++
> 2 files changed, 108 insertions(+)
>
> diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
> index ff1226485983..183798b81496 100644
> --- a/hw/intc/pnv_xive.c
> +++ b/hw/intc/pnv_xive.c
> @@ -390,6 +390,80 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t
> blk, uint32_t idx,
> return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas);
> }
>
> +static int cpu_pir(PowerPCCPU *cpu)
> +{
> + CPUPPCState *env = &cpu->env;
> + return env->spr_cb[SPR_PIR].default_value;
> +}
> +
> +static int cpu_chip_id(PowerPCCPU *cpu)
> +{
> + int pir = cpu_pir(cpu);
> + return (pir >> 8) & 0x7f;
> +}
> +
> +static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu)
> +{
> + int pir = cpu_pir(cpu);
> + int thrd_id = pir & 0x7f;
> +
> + return xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(thrd_id);
> +}
> +
> +static bool pnv_xive_is_ignored(PnvChip *chip, CPUState *cs)
> +{
> + return chip->chip_id != cpu_chip_id(POWERPC_CPU(cs));
> +}
> +
> +#define PNV_CHIP_CPU_FOREACH(chip, cs) \
> + CPU_FOREACH(cs) \
> + if (pnv_xive_is_ignored(chip, cs)) {} else
patchew will complain here but I think we can consider it as an exception
since it is inspired from the macros in migration/ram.c ?
Thanks,
C.
- [Qemu-devel] [PATCH v3 00/18] ppc/pnv: add XIVE support for KVM guests, Cédric Le Goater, 2019/07/31
- [Qemu-devel] [PATCH v3 01/18] ppc/pnv: Introduce PowerNV machines with fixed CPU models, Cédric Le Goater, 2019/07/31
- [Qemu-devel] [PATCH v3 02/18] tests/boot-serial-test: add support for all the PowerNV machines, Cédric Le Goater, 2019/07/31
- [Qemu-devel] [PATCH v3 03/18] ppc/xive: Introduce the XiveFabric and XivePresenter interfaces, Cédric Le Goater, 2019/07/31
- [Qemu-devel] [PATCH v3 04/18] ppc/pnv: Implement the XiveFabric and XivePresenter interfaces, Cédric Le Goater, 2019/07/31
- Re: [Qemu-devel] [PATCH v3 04/18] ppc/pnv: Implement the XiveFabric and XivePresenter interfaces,
Cédric Le Goater <=
- [Qemu-devel] [PATCH v3 05/18] ppc/spapr: Implement the XiveFabric and XivePresenter interfaces, Cédric Le Goater, 2019/07/31
- [Qemu-devel] [PATCH v3 06/18] ppc/xive: Use the XiveFabric and XivePresenter interfaces, Cédric Le Goater, 2019/07/31
- [Qemu-devel] [PATCH v3 07/18] ppc/xive: Extend the TIMA operation with a XivePresenter parameter, Cédric Le Goater, 2019/07/31
- [Qemu-devel] [PATCH v3 08/18] ppc/pnv: Clarify how the TIMA is accessed on a multichip system, Cédric Le Goater, 2019/07/31
- [Qemu-devel] [PATCH v3 09/18] ppc/xive: Move the TIMA operations to the controller model, Cédric Le Goater, 2019/07/31
- [Qemu-devel] [PATCH v3 10/18] ppc/xive: Introduce a xive_tctx_ipb_update() helper, Cédric Le Goater, 2019/07/31
- [Qemu-devel] [PATCH v3 11/18] ppc/xive: Synthesize interrupt from the saved IPB in the NVT, Cédric Le Goater, 2019/07/31
- [Qemu-devel] [PATCH v3 12/18] ppc/pnv: Remove pnv_xive_vst_size() routine, Cédric Le Goater, 2019/07/31
- [Qemu-devel] [PATCH v3 13/18] ppc/pnv: Dump the XIVE NVT table, Cédric Le Goater, 2019/07/31
- [Qemu-devel] [PATCH v3 14/18] ppc/pnv: Skip empty slots of the XIVE NVT table, Cédric Le Goater, 2019/07/31