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[Qemu-devel] [PATCH v2 21/28] riscv: sifive_u: Update UART and ethernet
From: |
Bin Meng |
Subject: |
[Qemu-devel] [PATCH v2 21/28] riscv: sifive_u: Update UART and ethernet node clock properties |
Date: |
Wed, 7 Aug 2019 00:45:17 -0700 |
Now that we have added PRCI nodes, update existing UART and ethernet
nodes to use PRCI as their clock sources, to keep in sync with the
Linux kernel device tree.
With above changes, the previously handcrafted "/soc/ethclk" node is
no longer needed. Remove it.
Signed-off-by: Bin Meng <address@hidden>
---
Changes in v2: None
hw/riscv/sifive_u.c | 21 +++++----------------
include/hw/riscv/sifive_u.h | 3 +--
include/hw/riscv/sifive_u_prci.h | 10 ++++++++++
3 files changed, 16 insertions(+), 18 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7b4a684..fb4845c 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -82,8 +82,8 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
int cpu;
uint32_t *cells;
char *nodename;
- char ethclk_names[] = "pclk\0hclk\0tx_clk";
- uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1;
+ char ethclk_names[] = "pclk\0hclk";
+ uint32_t plic_phandle, prci_phandle, phandle = 1;
uint32_t hfclk_phandle, rtcclk_phandle;
fdt = s->fdt = create_device_tree(&s->fdt_size);
@@ -242,17 +242,6 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
g_free(cells);
g_free(nodename);
- ethclk_phandle = phandle++;
- nodename = g_strdup_printf("/soc/ethclk");
- qemu_fdt_add_subnode(fdt, nodename);
- qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
- qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
- qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
- SIFIVE_U_GEM_CLOCK_FREQ);
- qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle);
- ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
- g_free(nodename);
-
nodename = g_strdup_printf("/soc/ethernet@%lx",
(long)memmap[SIFIVE_U_GEM].base);
qemu_fdt_add_subnode(fdt, nodename);
@@ -265,7 +254,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
- ethclk_phandle, ethclk_phandle, ethclk_phandle);
+ prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names,
sizeof(ethclk_names));
qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
@@ -285,8 +274,8 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[SIFIVE_U_UART0].base,
0x0, memmap[SIFIVE_U_UART0].size);
- qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
- SIFIVE_U_CLOCK_FREQ / 2);
+ qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+ prci_phandle, PRCI_CLK_TLCLK);
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 2f475c5..0461331 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -68,8 +68,7 @@ enum {
enum {
SIFIVE_U_CLOCK_FREQ = 1000000000,
SIFIVE_U_HFCLK_FREQ = 33333333,
- SIFIVE_U_RTCCLK_FREQ = 1000000,
- SIFIVE_U_GEM_CLOCK_FREQ = 125000000
+ SIFIVE_U_RTCCLK_FREQ = 1000000
};
#define SIFIVE_U_PLIC_HART_CONFIG "MS"
diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/riscv/sifive_u_prci.h
index f3a4656..640c641 100644
--- a/include/hw/riscv/sifive_u_prci.h
+++ b/include/hw/riscv/sifive_u_prci.h
@@ -87,4 +87,14 @@ typedef struct SiFivePRCIState {
DeviceState *sifive_u_prci_create(hwaddr addr);
+/*
+ * Clock indexes for use by Device Tree data and the PRCI driver.
+ *
+ * These values are from sifive-fu540-prci.h in the Linux kernel.
+ */
+#define PRCI_CLK_COREPLL 0
+#define PRCI_CLK_DDRPLL 1
+#define PRCI_CLK_GEMGXLPLL 2
+#define PRCI_CLK_TLCLK 3
+
#endif /* HW_SIFIVE_U_PRCI_H */
--
2.7.4
- Re: [Qemu-devel] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, (continued)
[Qemu-devel] [PATCH v2 13/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 14/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 16/28] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 18/28] riscv: hw: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 17/28] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 21/28] riscv: sifive_u: Update UART and ethernet node clock properties,
Bin Meng <=
[Qemu-devel] [PATCH v2 22/28] riscv: sifive_u: Generate an aliases node in the device tree, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 24/28] riscv: sifive_u: Support loading initramfs, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 25/28] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 28/28] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 27/28] riscv: virt: Change create_fdt() to return void, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 23/28] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/07