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[Qemu-devel] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong |
Date: |
Thu, 15 Aug 2019 14:35:04 -0700 |
The mip register is an MXLEN-bit long register. Convert it to a
target_ulong type instead of uint32_t.
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2dc9b17678..0a7985c3f7 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -130,7 +130,7 @@ struct CPURISCVState {
* wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero.
* mip is 32-bits to allow atomic_read on 32-bit hosts.
*/
- uint32_t mip;
+ target_ulong mip;
uint32_t miclaim;
target_ulong mie;
--
2.22.0
- [Qemu-devel] [PATCH v3 3/7] target/riscv: Create function to test if FP is enabled, (continued)
- [Qemu-devel] [PATCH v3 3/7] target/riscv: Create function to test if FP is enabled, Alistair Francis, 2019/08/15
- [Qemu-devel] [PATCH v3 2/7] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/08/15
- [Qemu-devel] [PATCH v3 4/7] target/riscv: Update the Hypervisor CSRs to v0.4, Alistair Francis, 2019/08/15
- [Qemu-devel] [PATCH v3 5/7] target/riscv: Use both register name and ABI name, Alistair Francis, 2019/08/15
- [Qemu-devel] [PATCH v3 6/7] target/riscv: Fix mstatus dirty mask, Alistair Francis, 2019/08/15
- [Qemu-devel] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong,
Alistair Francis <=
- Re: [Qemu-devel] [PATCH v3 0/7] RISC-V: Hypervisor prep work part 2, no-reply, 2019/08/15