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[Qemu-devel] [PULL 25/29] target/arm: Remove redundant shift tests
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 25/29] target/arm: Remove redundant shift tests |
Date: |
Fri, 16 Aug 2019 14:17:15 +0100 |
From: Richard Henderson <address@hidden>
The immediate shift generator functions already test for,
and eliminate, the case of a shift by zero.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate.c | 19 +++++++------------
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9c3323509e1..ebc7c67f025 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8811,8 +8811,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int
insn)
shift = (insn >> 10) & 3;
/* ??? In many cases it's not necessary to do a
rotate, a shift is sufficient. */
- if (shift != 0)
- tcg_gen_rotri_i32(tmp, tmp, shift * 8);
+ tcg_gen_rotri_i32(tmp, tmp, shift * 8);
op1 = (insn >> 20) & 7;
switch (op1) {
case 0: gen_sxtb16(tmp); break;
@@ -9889,8 +9888,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t
insn)
shift = (insn >> 4) & 3;
/* ??? In many cases it's not necessary to do a
rotate, a shift is sufficient. */
- if (shift != 0)
- tcg_gen_rotri_i32(tmp, tmp, shift * 8);
+ tcg_gen_rotri_i32(tmp, tmp, shift * 8);
op = (insn >> 20) & 7;
switch (op) {
case 0: gen_sxth(tmp); break;
@@ -10617,11 +10615,10 @@ static void disas_thumb2_insn(DisasContext *s,
uint32_t insn)
case 7:
goto illegal_op;
default: /* Saturate. */
- if (shift) {
- if (op & 1)
- tcg_gen_sari_i32(tmp, tmp, shift);
- else
- tcg_gen_shli_i32(tmp, tmp, shift);
+ if (op & 1) {
+ tcg_gen_sari_i32(tmp, tmp, shift);
+ } else {
+ tcg_gen_shli_i32(tmp, tmp, shift);
}
tmp2 = tcg_const_i32(imm);
if (op & 4) {
@@ -10812,9 +10809,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t
insn)
goto illegal_op;
}
tmp = load_reg(s, rm);
- if (shift) {
- tcg_gen_shli_i32(tmp, tmp, shift);
- }
+ tcg_gen_shli_i32(tmp, tmp, shift);
tcg_gen_add_i32(addr, addr, tmp);
tcg_temp_free_i32(tmp);
break;
--
2.20.1
- [Qemu-devel] [PULL 10/29] target/arm: Remove redundant s->pc & ~1, (continued)
- [Qemu-devel] [PULL 10/29] target/arm: Remove redundant s->pc & ~1, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 11/29] target/arm: Replace s->pc with s->base.pc_next, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 15/29] target/arm: Use unallocated_encoding for aarch32, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 12/29] target/arm: Replace offset with pc in gen_exception_insn, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 18/29] target/arm/cpu: Ensure we can use the pmu with kvm, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 20/29] target/arm/cpu: Use div-round-up to determine predicate register array size, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 21/29] target/arm/kvm64: Fix error returns, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 24/29] target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 27/29] target/arm: Use tcg_gen_rotri_i32 for gen_swap_half, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 23/29] target/arm: Use tcg_gen_extract_i32 for shifter_out_im, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 25/29] target/arm: Remove redundant shift tests,
Peter Maydell <=
- [Qemu-devel] [PULL 22/29] target/arm/kvm64: Move the get/put of fpsimd registers out, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 26/29] target/arm: Use ror32 instead of open-coding the operation, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 28/29] target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 29/29] target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word, Peter Maydell, 2019/08/16
- Re: [Qemu-devel] [PULL 00/29] target-arm queue, Peter Maydell, 2019/08/16