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Re: [Qemu-devel] [PATCH v2 18/68] target/arm: Convert the rest of A32 Mi
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From: |
Peter Maydell |
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Subject: |
Re: [Qemu-devel] [PATCH v2 18/68] target/arm: Convert the rest of A32 Miscelaneous instructions |
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Date: |
Fri, 23 Aug 2019 13:03:41 +0100 |
On Mon, 19 Aug 2019 at 22:38, Richard Henderson
<address@hidden> wrote:
In subject, typo: "Miscellaneous".
> This fixes an exiting bug with the T5 encoding of SUBS PC, LR, #IMM,
"existing"
> in that it may be executed from user mode as with any other encoding
> of SUBS, not as ERET.
Should this paragraph be in the commit message for the previous
patch? This change doesn't touch SUBS/ERET.
Otherwise
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
- [Qemu-devel] [PATCH v2 13/68] target/arm: Convert MRS/MSR (banked, register), (continued)
- [Qemu-devel] [PATCH v2 13/68] target/arm: Convert MRS/MSR (banked, register), Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 15/68] target/arm: Convert BX, BXJ, BLX (register), Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 17/68] target/arm: Convert ERET, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 14/68] target/arm: Convert Cyclic Redundancy Check, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 18/68] target/arm: Convert the rest of A32 Miscelaneous instructions, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 16/68] target/arm: Convert CLZ, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 19/68] target/arm: Convert T32 ADDW/SUBW, Richard Henderson, 2019/08/19