Re: [Qemu-devel] [PATCH 06/13] target/openrisc: Add VR2 and AVR special processor registers

[Stafford Horne]

On Mon, Aug 26, 2019 at 05:07:38PM -0700, Richard Henderson wrote:
> Update the CPUCFG bits to arch v1.3.
> Include support for AVRP for cpu "any".
> 
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target/openrisc/cpu.h        | 11 +++++++----
>  target/openrisc/cpu.c        |  8 ++++++--
>  target/openrisc/sys_helper.c |  6 ++++++
>  3 files changed, 19 insertions(+), 6 deletions(-)
> 
> diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
> index 18d7445e74..71c5959828 100644
> --- a/target/openrisc/cpu.h
> +++ b/target/openrisc/cpu.h
> @@ -96,11 +96,12 @@ enum {
>      CPUCFGR_OF32S = (1 << 7),
>      CPUCFGR_OF64S = (1 << 8),
>      CPUCFGR_OV64S = (1 << 9),
> -    /* CPUCFGR_ND = (1 << 10), */
> -    /* CPUCFGR_AVRP = (1 << 11), */
> +    CPUCFGR_ND = (1 << 10),
> +    CPUCFGR_AVRP = (1 << 11),
>      CPUCFGR_EVBARP = (1 << 12),
> -    /* CPUCFGR_ISRP = (1 << 13), */
> -    /* CPUCFGR_AECSRP = (1 << 14), */
> +    CPUCFGR_ISRP = (1 << 13),
> +    CPUCFGR_AECSRP = (1 << 14),
> +    CPUCFGR_OF64A32S = (1 << 15),
>  };
>  
>  /* DMMU configure register */
> @@ -280,6 +281,8 @@ typedef struct CPUOpenRISCState {
>  
>      /* Fields from here on are preserved across CPU reset. */
>      uint32_t vr;              /* Version register */
> +    uint32_t vr2;             /* Version register 2 */
> +    uint32_t avr;             /* Architecture version register */

Do you need to update the serialization in machine.c?