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[Qemu-devel] [PATCH 17/36] cputlb: Byte swap memory transaction attribut
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 17/36] cputlb: Byte swap memory transaction attribute |
Date: |
Tue, 3 Sep 2019 09:08:39 -0700 |
From: Tony Nguyen <address@hidden>
Notice new attribute, byte swap, and force the transaction through the
memory slow path.
Required by architectures that can invert endianness of memory
transaction, e.g. SPARC64 has the Invert Endian TTE bit.
Suggested-by: Richard Henderson <address@hidden>
Signed-off-by: Tony Nguyen <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
include/exec/memattrs.h | 2 ++
accel/tcg/cputlb.c | 12 ++++++++++++
2 files changed, 14 insertions(+)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index d4a3477d71..95f2d20d55 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -37,6 +37,8 @@ typedef struct MemTxAttrs {
unsigned int user:1;
/* Requester ID (for MSI for example) */
unsigned int requester_id:16;
+ /* Invert endianness for this page */
+ unsigned int byte_swap:1;
/*
* The following are target-specific page-table bits. These are not
* related to actual memory transactions at all. However, this structure
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 3c9e634d99..d9787cc893 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -738,6 +738,10 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong
vaddr,
*/
address |= TLB_RECHECK;
}
+ if (attrs.byte_swap) {
+ /* Force the access through the I/O slow path. */
+ address |= TLB_MMIO;
+ }
if (!memory_region_is_ram(section->mr) &&
!memory_region_is_romd(section->mr)) {
/* IO memory case */
@@ -891,6 +895,10 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry
*iotlbentry,
bool locked = false;
MemTxResult r;
+ if (iotlbentry->attrs.byte_swap) {
+ op ^= MO_BSWAP;
+ }
+
section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
mr = section->mr;
mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
@@ -933,6 +941,10 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry
*iotlbentry,
bool locked = false;
MemTxResult r;
+ if (iotlbentry->attrs.byte_swap) {
+ op ^= MO_BSWAP;
+ }
+
section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
mr = section->mr;
mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
--
2.17.1
- [Qemu-devel] [PATCH 12/36] target/mips: Hard code size with MO_{8|16|32|64}, (continued)
- [Qemu-devel] [PATCH 12/36] target/mips: Hard code size with MO_{8|16|32|64}, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 13/36] exec: Hard code size with MO_{8|16|32|64}, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 01/36] tcg: TCGMemOp is now accelerator independent MemOp, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 15/36] cputlb: Replace size and endian operands for MemOp, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 14/36] memory: Access MemoryRegion with endianness, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 16/36] memory: Single byte swap along the I/O path, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 19/36] target/sparc: sun4u Invert Endian TTE bit, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 18/36] target/sparc: Add TLB entry with attributes, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 20/36] exec: Move user-only watchpoint stubs inline, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 21/36] exec: Factor out core logic of check_watchpoint(), Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 17/36] cputlb: Byte swap memory transaction attribute,
Richard Henderson <=
- [Qemu-devel] [PATCH 24/36] cputlb: Fix size operand for tlb_fill on unaligned store, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 23/36] exec: Factor out cpu_watchpoint_address_matches, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 22/36] cputlb: Fold TLB_RECHECK into TLB_INVALID_MASK, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 25/36] cputlb: Remove double-alignment in store_helper, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 27/36] tcg: Check for watchpoints in probe_write(), Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 29/36] s390x/tcg: Fix length calculation in probe_write_access(), Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 26/36] cputlb: Handle watchpoints via TLB_WATCHPOINT, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 28/36] s390x/tcg: Use guest_addr_valid() instead of h2g_valid() in probe_write_access(), Richard Henderson, 2019/09/03