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[Qemu-devel] [PATCH v2 2/5] target/arm: handle A-profile T32 semihosting
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [PATCH v2 2/5] target/arm: handle A-profile T32 semihosting at translate time |
Date: |
Wed, 4 Sep 2019 12:21:05 +0100 |
As for the other semihosting calls we can resolve this at translate
time.
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
v2
- update for change to gen_exception_internal_insn API
---
target/arm/translate.c | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 816d46b2205..673994ed1a1 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10949,6 +10949,24 @@ static inline void gen_thumb_bkpt(DisasContext *s, int
imm8)
gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true));
}
+/*
+ * Thumb SWI. On A-profile CPUs this may be a semihosting call.
+ */
+static inline void gen_thumb_swi(DisasContext *s, int imm8)
+{
+ if (semihosting_enabled() &&
+#ifndef CONFIG_USER_ONLY
+ s->current_el != 0 &&
+#endif
+ (imm8 == 0xab)) {
+ gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
+ return;
+ }
+ gen_set_pc_im(s, s->base.pc_next);
+ s->svc_imm = imm8;
+ s->base.is_jmp = DISAS_SWI;
+}
+
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{
uint32_t val, op, rm, rn, rd, shift, cond;
@@ -11700,10 +11718,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
goto undef;
if (cond == 0xf) {
- /* swi */
- gen_set_pc_im(s, s->base.pc_next);
- s->svc_imm = extract32(insn, 0, 8);
- s->base.is_jmp = DISAS_SWI;
+ /* swi/svc */
+ gen_thumb_swi(s, extract32(insn, 0, 8));
break;
}
/* generate a conditional jump to next instruction */
--
2.20.1
- [Qemu-devel] [PATCH v2 0/5] fixed up semihosting fixups, Alex Bennée, 2019/09/04
- [Qemu-devel] [PATCH v2 2/5] target/arm: handle A-profile T32 semihosting at translate time,
Alex Bennée <=
- [Qemu-devel] [PATCH v2 1/5] target/arm: handle M-profile semihosting at translate time, Alex Bennée, 2019/09/04
- [Qemu-devel] [PATCH v2 3/5] target/arm: handle A-profile A32 semihosting at translate time, Alex Bennée, 2019/09/04
- [Qemu-devel] [PATCH v2 5/5] atomic_template: fix indentation in GEN_ATOMIC_HELPER, Alex Bennée, 2019/09/04
- [Qemu-devel] [PATCH v2 4/5] target/arm: remove run time semihosting checks, Alex Bennée, 2019/09/04
- Re: [Qemu-devel] [PATCH v2 0/5] fixed up semihosting fixups, Peter Maydell, 2019/09/06