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[Qemu-devel] [PATCH v8 08/32] riscv: hw: Remove the unnecessary include
From: |
Bin Meng |
Subject: |
[Qemu-devel] [PATCH v8 08/32] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h |
Date: |
Fri, 6 Sep 2019 09:19:55 -0700 |
The inclusion of "target/riscv/cpu.h" is unnecessary in various
sifive model drivers.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- new patch to remove the unnecessary include of target/riscv/cpu.h
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_prci.c | 1 -
hw/riscv/sifive_test.c | 1 -
hw/riscv/sifive_uart.c | 1 -
3 files changed, 3 deletions(-)
diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c
index 982fbb2..c413f0c 100644
--- a/hw/riscv/sifive_prci.c
+++ b/hw/riscv/sifive_prci.c
@@ -22,7 +22,6 @@
#include "hw/sysbus.h"
#include "qemu/log.h"
#include "qemu/module.h"
-#include "target/riscv/cpu.h"
#include "hw/hw.h"
#include "hw/riscv/sifive_prci.h"
diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
index aa544e7..339195c 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/riscv/sifive_test.c
@@ -23,7 +23,6 @@
#include "qemu/log.h"
#include "qemu/module.h"
#include "sysemu/runstate.h"
-#include "target/riscv/cpu.h"
#include "hw/hw.h"
#include "hw/riscv/sifive_test.h"
diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c
index 215990b..a403ae9 100644
--- a/hw/riscv/sifive_uart.c
+++ b/hw/riscv/sifive_uart.c
@@ -22,7 +22,6 @@
#include "hw/sysbus.h"
#include "chardev/char.h"
#include "chardev/char-fe.h"
-#include "target/riscv/cpu.h"
#include "hw/hw.h"
#include "hw/irq.h"
#include "hw/riscv/sifive_uart.h"
--
2.7.4
- [Qemu-devel] [PATCH v8 00/32] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Bin Meng, 2019/09/06
- [Qemu-devel] [PATCH v8 01/32] riscv: hw: Remove duplicated "hw/hw.h" inclusion, Bin Meng, 2019/09/06
- [Qemu-devel] [PATCH v8 02/32] riscv: sifive_test: Add reset functionality, Bin Meng, 2019/09/06
- [Qemu-devel] [PATCH v8 05/32] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/09/06
- [Qemu-devel] [PATCH v8 03/32] riscv: hw: Remove superfluous "linux, phandle" property, Bin Meng, 2019/09/06
- [Qemu-devel] [PATCH v8 04/32] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/09/06
- [Qemu-devel] [PATCH v8 07/32] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead, Bin Meng, 2019/09/06
- [Qemu-devel] [PATCH v8 08/32] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h,
Bin Meng <=
- [Qemu-devel] [PATCH v8 09/32] riscv: roms: Remove executable attribute of opensbi images, Bin Meng, 2019/09/06
- [Qemu-devel] [PATCH v8 06/32] riscv: hw: Change create_fdt() to return void, Bin Meng, 2019/09/06
- [Qemu-devel] [PATCH v8 10/32] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/09/06
- [Qemu-devel] [PATCH v8 12/32] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/09/06
- [Qemu-devel] [PATCH v8 11/32] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/09/06
- [Qemu-devel] [PATCH v8 14/32] riscv: sifive_e: Drop sifive_mmio_emulate(), Bin Meng, 2019/09/06
- [Qemu-devel] [PATCH v8 13/32] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/09/06
- [Qemu-devel] [PATCH v8 15/32] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/09/06
- [Qemu-devel] [PATCH v8 16/32] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/09/06