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[Qemu-devel] [PULL 41/47] riscv: sifive_u: Instantiate OTP memory with a
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PULL 41/47] riscv: sifive_u: Instantiate OTP memory with a serial number |
Date: |
Tue, 10 Sep 2019 12:05:07 -0700 |
From: Bin Meng <address@hidden>
This adds an OTP memory with a given serial number to the sifive_u
machine. With such support, the upstream U-Boot for sifive_fu540
boots out of the box on the sifive_u machine.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 9 +++++++++
include/hw/riscv/sifive_u.h | 3 +++
2 files changed, 12 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 5ca3793d35..4803e47ae4 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -10,6 +10,7 @@
* 1) CLINT (Core Level Interruptor)
* 2) PLIC (Platform Level Interrupt Controller)
* 3) PRCI (Power, Reset, Clock, Interrupt)
+ * 4) OTP (One-Time Programmable) memory with stored serial number
*
* This board currently generates devicetree dynamically that indicates at
least
* two harts and up to five harts.
@@ -64,10 +65,12 @@ static const struct MemmapEntry {
[SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
[SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
[SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
+ [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
[SIFIVE_U_GEM] = { 0x100900FC, 0x2000 },
};
+#define OTP_SERIAL 1
#define GEM_REVISION 0x10070109
static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
@@ -422,6 +425,9 @@ static void riscv_sifive_u_soc_init(Object *obj)
sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci),
TYPE_SIFIVE_U_PRCI);
+ sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
+ TYPE_SIFIVE_U_OTP);
+ qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL);
sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
TYPE_CADENCE_GEM);
}
@@ -498,6 +504,9 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev,
Error **errp)
object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
+ object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
+
for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
}
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 7dfd1cb22e..4d4733cb6a 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -23,6 +23,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_cpu.h"
#include "hw/riscv/sifive_u_prci.h"
+#include "hw/riscv/sifive_u_otp.h"
#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
#define RISCV_U_SOC(obj) \
@@ -39,6 +40,7 @@ typedef struct SiFiveUSoCState {
RISCVHartArrayState u_cpus;
DeviceState *plic;
SiFiveUPRCIState prci;
+ SiFiveUOTPState otp;
CadenceGEMState gem;
} SiFiveUSoCState;
@@ -60,6 +62,7 @@ enum {
SIFIVE_U_PRCI,
SIFIVE_U_UART0,
SIFIVE_U_UART1,
+ SIFIVE_U_OTP,
SIFIVE_U_DRAM,
SIFIVE_U_GEM
};
--
2.21.0
- [Qemu-devel] [PULL 30/47] riscv: sifive_u: Set the minimum number of cpus to 2, (continued)
- [Qemu-devel] [PULL 30/47] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 32/47] riscv: sifive_u: Update PLIC hart topology configuration string, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 29/47] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 31/47] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 34/47] riscv: sifive_u: Generate hfclk and rtcclk nodes, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 35/47] riscv: sifive_u: Add PRCI block to the SoC, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 36/47] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 33/47] riscv: sifive: Implement PRCI model for FU540, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 37/47] riscv: sifive_u: Update UART base addresses and IRQs, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 38/47] riscv: sifive_u: Change UART node name in device tree, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 41/47] riscv: sifive_u: Instantiate OTP memory with a serial number,
Palmer Dabbelt <=
- [Qemu-devel] [PULL 40/47] riscv: sifive: Implement a model for SiFive FU540 OTP, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 43/47] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 39/47] riscv: roms: Update default bios for sifive_u machine, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 42/47] riscv: sifive_u: Fix broken GEM support, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 44/47] riscv: sifive_u: Update model and compatible strings in device tree, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 45/47] target/riscv: Use both register name and ABI name, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 47/47] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 46/47] target/riscv: Fix mstatus dirty mask, Palmer Dabbelt, 2019/09/11
- Re: [Qemu-devel] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, Peter Maydell, 2019/09/13