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Re: [Qemu-devel] [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the
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From: |
Bin Meng |
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Subject: |
Re: [Qemu-devel] [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2 |
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Date: |
Mon, 16 Sep 2019 15:51:11 +0800 |
Hi Jonathan,
On Mon, Sep 16, 2019 at 1:40 AM Jonathan Behrens <address@hidden> wrote:
>
> Has there been testing with "-smp 2"? A while back I thought I read that the
> included uboot firmware was using a hard-coded device tree that indicated 4+1
> CPUs, which I would have expected to cause Linux boot issues?
>
No, U-Boot is using DTB that was passed from previous stage firmware - OpenSBI.
On a real board this is 4 + 1. On QEMU, DTB is dynamically generated
per "-smp n" settings. So there should be no problem.
Regards,
Bin
- [Qemu-devel] [PATCH v8 15/32] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, (continued)
- [Qemu-devel] [PATCH v8 15/32] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/09/06
- [Qemu-devel] [PATCH v8 16/32] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/09/06
- [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/09/06
- Re: [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/13
- Re: [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/09/13
- Re: [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/14
- Re: [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/09/15
- Re: [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/15
- Re: [Qemu-devel] [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Jonathan Behrens, 2019/09/15
- Re: [Qemu-devel] [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/15
- Re: [Qemu-devel] [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2,
Bin Meng <=
- Re: [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Alistair Francis, 2019/09/16
[Qemu-devel] [PATCH v8 22/32] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/09/06
[Qemu-devel] [PATCH v8 17/32] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Bin Meng, 2019/09/06
[Qemu-devel] [PATCH v8 20/32] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/09/06
[Qemu-devel] [PATCH v8 21/32] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/09/06
[Qemu-devel] [PATCH v8 24/32] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Bin Meng, 2019/09/06
[Qemu-devel] [PATCH v8 19/32] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/09/06
[Qemu-devel] [PATCH v8 26/32] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/09/06
[Qemu-devel] [PATCH v8 25/32] riscv: sifive_u: Update UART base addresses and IRQs, Bin Meng, 2019/09/06