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Re: [PATCH] hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots
From: |
Richard Henderson |
Subject: |
Re: [PATCH] hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots |
Date: |
Fri, 20 Sep 2019 14:59:29 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 |
On 9/20/19 10:40 AM, Peter Maydell wrote:
> If we're booting a Linux kernel directly into Non-Secure
> state on a CPU which has Secure state, then make sure we
> set the NSACR CP11 and CP10 bits, so that Non-Secure is allowed
> to access the FPU. Otherwise an AArch32 kernel will UNDEF as
> soon as it tries to use the FPU.
>
> It used to not matter that we didn't do this until commit
> fc1120a7f5f2d4b6, where we implemented actually honouring
> these NSACR bits.
>
> The problem only exists for CPUs where EL3 is AArch32; the
> equivalent AArch64 trap bits are in CPTR_EL3 and are "0 to
> not trap, 1 to trap", so the reset value of the register
> permits NS access, unlike NSACR.
>
> Fixes: fc1120a7f5
> Fixes: https://bugs.launchpad.net/qemu/+bug/1844597
> Cc: address@hidden
> Signed-off-by: Peter Maydell <address@hidden>
> ---
Reviewed-by: Richard Henderson <address@hidden>
r~