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[PULL 4/9] target/arm: handle A-profile semihosting at translate time
From: |
Peter Maydell |
Subject: |
[PULL 4/9] target/arm: handle A-profile semihosting at translate time |
Date: |
Fri, 27 Sep 2019 15:42:44 +0100 |
From: Alex Bennée <address@hidden>
As for the other semihosting calls we can resolve this at translate
time.
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate.c | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index b5272119330..698c594e8ce 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10222,14 +10222,25 @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a)
}
/*
- * Supervisor call
+ * Supervisor call - both T32 & A32 come here so we need to check
+ * which mode we are in when checking for semihosting.
*/
static bool trans_SVC(DisasContext *s, arg_SVC *a)
{
- gen_set_pc_im(s, s->base.pc_next);
- s->svc_imm = a->imm;
- s->base.is_jmp = DISAS_SWI;
+ const uint32_t semihost_imm = s->thumb ? 0xab : 0x123456;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_M) && semihosting_enabled() &&
+#ifndef CONFIG_USER_ONLY
+ !IS_USER(s) &&
+#endif
+ (a->imm == semihost_imm)) {
+ gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
+ } else {
+ gen_set_pc_im(s, s->base.pc_next);
+ s->svc_imm = a->imm;
+ s->base.is_jmp = DISAS_SWI;
+ }
return true;
}
--
2.20.1
- [PULL 0/9] target-arm queue, Peter Maydell, 2019/09/27
- [PULL 2/9] tests/tcg: clean-up some comments after the de-tangling, Peter Maydell, 2019/09/27
- [PULL 3/9] target/arm: handle M-profile semihosting at translate time, Peter Maydell, 2019/09/27
- [PULL 4/9] target/arm: handle A-profile semihosting at translate time,
Peter Maydell <=
- [PULL 9/9] hw/arm/boot: Use the IEC binary prefix definitions, Peter Maydell, 2019/09/27
- [PULL 1/9] target/arm: fix CBAR register for AArch64 CPUs, Peter Maydell, 2019/09/27
- [PULL 7/9] tests/tcg: add linux-user semihosting smoke test for ARM, Peter Maydell, 2019/09/27
- [PULL 8/9] hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots, Peter Maydell, 2019/09/27
- [PULL 5/9] target/arm: remove run time semihosting checks, Peter Maydell, 2019/09/27
- [PULL 6/9] target/arm: remove run-time semihosting checks for linux-user, Peter Maydell, 2019/09/27
- Re: [PULL 0/9] target-arm queue, Peter Maydell, 2019/09/30