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[PULL 1/9] target/arm: fix CBAR register for AArch64 CPUs
From: |
Peter Maydell |
Subject: |
[PULL 1/9] target/arm: fix CBAR register for AArch64 CPUs |
Date: |
Fri, 27 Sep 2019 15:42:41 +0100 |
From: Luc Michel <address@hidden>
For AArch64 CPUs with a CBAR register, we have two views for it:
- in AArch64 state, the CBAR_EL1 register (S3_1_C15_C3_0), returns the
full 64 bits CBAR value
- in AArch32 state, the CBAR register (cp15, opc1=1, CRn=15, CRm=3, opc2=0)
returns a 32 bits view such that:
CBAR = CBAR_EL1[31:18] 0..0 CBAR_EL1[43:32]
This commit fixes the current implementation where:
- CBAR_EL1 was returning the 32 bits view instead of the full 64 bits
value,
- CBAR was returning a truncated 32 bits version of the full 64 bits
one, instead of the 32 bits view
- CBAR was declared as cp15, opc1=4, CRn=15, CRm=0, opc2=0, which is
the CBAR register found in the ARMv7 Cortex-Ax CPUs, but not in
ARMv8 CPUs.
Signed-off-by: Luc Michel <address@hidden>
Message-id: address@hidden
[PMM: Added a comment about the two different kinds of CBAR]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 507026c9154..bc1130d989d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6733,6 +6733,19 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
if (arm_feature(env, ARM_FEATURE_CBAR)) {
+ /*
+ * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
+ * There are two flavours:
+ * (1) older 32-bit only cores have a simple 32-bit CBAR
+ * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
+ * 32-bit register visible to AArch32 at a different encoding
+ * to the "flavour 1" register and with the bits rearranged to
+ * be able to squash a 64-bit address into the 32-bit view.
+ * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
+ * in future if we support AArch32-only configs of some of the
+ * AArch64 cores we might need to add a specific feature flag
+ * to indicate cores with "flavour 2" CBAR.
+ */
if (arm_feature(env, ARM_FEATURE_AARCH64)) {
/* 32 bit view is [31:18] 0...0 [43:32]. */
uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
@@ -6740,12 +6753,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
ARMCPRegInfo cbar_reginfo[] = {
{ .name = "CBAR",
.type = ARM_CP_CONST,
- .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
- .access = PL1_R, .resetvalue = cpu->reset_cbar },
+ .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0,
+ .access = PL1_R, .resetvalue = cbar32 },
{ .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
.type = ARM_CP_CONST,
.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
- .access = PL1_R, .resetvalue = cbar32 },
+ .access = PL1_R, .resetvalue = cpu->reset_cbar },
REGINFO_SENTINEL
};
/* We don't implement a r/w 64 bit CBAR currently */
--
2.20.1
- [PULL 0/9] target-arm queue, Peter Maydell, 2019/09/27
- [PULL 2/9] tests/tcg: clean-up some comments after the de-tangling, Peter Maydell, 2019/09/27
- [PULL 3/9] target/arm: handle M-profile semihosting at translate time, Peter Maydell, 2019/09/27
- [PULL 4/9] target/arm: handle A-profile semihosting at translate time, Peter Maydell, 2019/09/27
- [PULL 9/9] hw/arm/boot: Use the IEC binary prefix definitions, Peter Maydell, 2019/09/27
- [PULL 1/9] target/arm: fix CBAR register for AArch64 CPUs,
Peter Maydell <=
- [PULL 7/9] tests/tcg: add linux-user semihosting smoke test for ARM, Peter Maydell, 2019/09/27
- [PULL 8/9] hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots, Peter Maydell, 2019/09/27
- [PULL 5/9] target/arm: remove run time semihosting checks, Peter Maydell, 2019/09/27
- [PULL 6/9] target/arm: remove run-time semihosting checks for linux-user, Peter Maydell, 2019/09/27
- Re: [PULL 0/9] target-arm queue, Peter Maydell, 2019/09/30